User guide

34 www.xilinx.com Virtex-5 FPGA Integrated Endpoint Block
UG197 (v1.5) July 22, 2009
Chapter 2: Integrated Endpoint Block Functionality
R
If LLKRXDSTREQN is deasserted in each of the three cycles, including initial assertion of
LLKRXSRCLASTREQN, then one more request is required to complete reception of the
current packet. To complete reception, the user must assert
LLKRXDSTREQN for one
subsequent cycle. See Figure 2-8.
LLKRXSRCLASTREQN remains asserted until three cycles
after the integrated Endpoint block has received the final request for the current RX packet.
Ports
Table 2-6 shows the ports of the Transaction Layer interface.
Figure 2-8: Transaction Layer Interface Receive Timing Diagram Showing a 3 DW Header and 6 DW Data
Payload
CRMUSERCLK
LLKRXDSTREQN
LLKRXSRCLASTREQN
LLKRXSRCRDYN
LLKRXVALIDN
LLKRXDATA
LLKRXSOFN
LLKRXEOFN
3+TL_RAM_READ_LATENCY
11 11 11 1100
H0 H1 H2 P0
P1 P2
P3 P4
P5 XX
00 00 01
UG197_c2_06_111906
Table 2-6: Transaction Layer Interface Ports
Port Direction
Clock
Domain
Description
LLKTCSTATUS[7:0]
Output user_clk Report the status of the eight traffic classes: 1 implies
initialized; 0 implies uninitialized.
LLKTXDATA[63:0]
Input user_clk Transaction Layer interface transmit data.
LLKTXSRCRDYN
Input user_clk Asserted (active Low) if the transmit source has data
available.
LLKTXDSTRDYN
Output user_clk Asserted (active Low) if the transmit destination has
space available on the selected channel.
LLKTXSRCDSCN
Input user_clk Transmit source Frame Discard (active Low).
Not supported. Must be tied High.