User guide

32 www.xilinx.com Virtex-5 FPGA Integrated Endpoint Block
UG197 (v1.5) July 22, 2009
Chapter 2: Integrated Endpoint Block Functionality
R
Receive Framing
The receive framing signals are similar to the transmit framing signals. In receive packets,
the header is always before the data.
LLKRXVALIDN = 00 on all valid cycles except the last
one. If the total number of 32-bit DWORDs (header plus payload) is odd,
LLKRXVALIDN is
01 on the last beat.
Receive Handshake
When a packet has been received into the RX buffer and confirmed as valid, the integrated
Endpoint block asserts the appropriate
LLKRXCHPOSTEDAVAILABLEN,
LLKRXCHNONPOSTEDAVAILABLEN, or LLKRXCHCOMPLETIONAVAILABLEN signal to
indicate the type of packet that has been received. In some cases, requesting a packet that
has been received can violate PCIe transaction ordering rules. The user application must
monitor the
LLKRXPREFERREDTYPE signal and follow the rules specified in “Ordering at
Reception,” page 67 before requesting a packet from the integrated Endpoint block.
The user application selects the traffic class and the traffic type to read by setting
LLKRXCHTC to select the traffic class, and LLKRXCHFIFO to select posted, non-posted, or
completion.
The user asserts the
LLKRXDSTREQN signal to request data from the integrated Endpoint
block. For each clock where
LLKRXDSTREQN is asserted, the integrated Endpoint block
asserts
LLKRXSRCRDYN for one clock after a minimum delay of 3 + TLRAMREADLATENCY.
The value of the
TLRAMREADLATENCY attribute is in the range [2 .. 6].
The receive interfaces provides a
LLKRXSRCRDYN signal when data is valid on
LLKRXDATA.
The integrated Endpoint block asserts
LLKRXSRCLASTREQN three user_clk cycles after it
has received the second-to-last (penultimate) request for the current RX packet via
LLKRXDSTREQN. A single assertion of LLKRXDSTREQN during the three user_clk cycles is
sufficient for the block to receive its final request for the current RX packet. Other
assertions of
LLKRXDSTREQN are ignored, provided LLKRXDSTCONTREQN is deasserted. If
the block has received the final request when
LLKRXSRCLASTREQN is asserted, no further
requests should be issued on subsequent cycles (via
LLKRXDSTREQN) unless there are
further packets available on the selected channel as indicated by the corresponding
LLKRX*AVAILABLEN signal (where * is POSTED, NONPOSTED, or COMPLETION). When
configuration packets are being processed, the
LLKRX*AVAILABLEN signals are deasserted
until processing of the configuration packet is complete.