User guide

28 www.xilinx.com Virtex-5 FPGA Integrated Endpoint Block

UG197 (v1.5) July 22, 2009

Chapter 2: Integrated Endpoint Block Functionality

Transaction Layer Interface

Packets are presented to and received from the integrated Endpoint block’s Transaction

Layer through the Transaction Layer interface. On this interface, a beat is a clock cycle

where both the source and destination are ready. The main Transaction Layer interface

framing signals indicate the start of frame, the end of frame, destination ready, and source

ready.

Transmit

The transmit portion of the interface accepts the data from the user application that is to be

transmitted to the link partner. Transaction Layer Packets (TLPs) for transmission need to

be created in accordance with the PCI Express Base Specification, then presented to the

integrated Endpoint block’s Transaction Layer interface.

Data

The data bus contains data for the packet header, payload, and digest, if present. The

header must be written before the data. The digest is treated as the last word of the data.

The presence of a TLP digest (ECRC) is indicated by setting the TD bit in the header to '1'.

For more information on creating the TLP digest, see Chapter 2 of the PCI Express Base

Specification.

Packets must be formed by the user in accordance with the PCI Express Base Specification,

and presented on the LLKTXDATA ports as shown in Table 2-4 and Table 2-5. The header

and data must be presented in the order shown, although they need not be presented on

consecutive clock cycles, as shown in the timing diagram in Figure 2-5.

The first header DW (32-bit DWORD) of a packet must always appear on

LLKTXDATA[63:32], and cannot appear in the same clock cycle as the final DW of the

previous packet (but can appear in the next clock cycle, if all other signaling requirements

are met).

Table 2-4: Byte Ordering on LLKTXDATA for 3 DW Header, 4 DW Payload

LLKTXDATA

63 56 55 48 47 40 39 32 31 24 23 16 15 8 7 0

byte0 byte1 byte2 byte3 byte4 byte5 byte6 byte7

Header DW0 Header DW1

Header DW2 Payload DW0

Payload DW1 Payload DW2

Payload DW3 don’t care

Table 2-5: Byte Ordering on LLKTXDATA for 4 DW Header, 4 DW Payload

LLKTXDATA

63 56 55 48 47 40 39 32 31 24 23 16 15 8 7 0

byte0 byte1 byte2 byte3 byte4 byte5 byte6 byte7

Header DW0 Header DW1

Header DW2 Header DW3

Payload DW0 Payload DW1

Payload DW2 Payload DW3