User guide

Virtex-5 FPGA Integrated Endpoint Block www.xilinx.com 27
UG197 (v1.5) July 22, 2009
Virtex-5 FPGA Integrated Endpoint Block Interface Descriptions
R
CRMDOHOTRESETN
Output core_clk Hot reset (active Low). Asserted on completion of hot reset
handshake as a prompt for user logic to be reset. See “Resets,”
page 23.
CRMPWRSOFTRESETN
Output core_clk Soft reset (active Low). Asserted when the block makes the
transition from D3
hot
to D0
uninitialized
, as a prompt for user logic
to be reset (with
CRMUSERCFGRSTN).
Table 2-3: Clock and Reset Ports (Continued)
Port Direction
Clock
Domain
Description