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24 www.xilinx.com Virtex-5 FPGA Integrated Endpoint Block

UG197 (v1.5) July 22, 2009

Chapter 2: Integrated Endpoint Block Functionality

During FPGA configuration, the entire integrated Endpoint block is reset, including the

sticky register block, the PCI Configuration Space, and the Management Interface

registers. All other resets of the block are controlled by the user through the six reset ports.

These signals are asynchronous, but there is logic in the integrated Endpoint block to

guarantee synchronous deassertion with respect to the core_clk. The integrated Endpoint

block must be clocked while its reset port(s) are asserted in order for the appropriate

portion(s) of the block to be reset.

The integrated Endpoint block asserts the

PIPERESETLn signals to all lanes when the

MAC_RST domain is reset. PIPERESETLn is only deasserted for the active lanes (based on

the

ACTIVELANESIN attribute setting) and remains asserted for the unused lanes. The

PIPERESETLn ports are connected to the RXCDRRESET port on the RocketIO transceivers.

See Table 2-14, page 43 for details.

The user reset design in fabric for the PCIe system must assert the appropriate reset signals

for warm reset, hot reset, DL_Down, etc. The user should also ensure that the integrated

Endpoint block is held in reset until the PLL is locked. This reset design is included in the

CORE Generator wrapper.

The falling edge of the

L0DLUPDOWN[0] output of the integrated Endpoint block indicates

when the link goes down (DL_Down status). The

CRMDOHOTRESETN output is asserted

when a hot reset is received from upstream. An Endpoint user design must use these

outputs to reset a portion of the integrated Endpoint block. This is done in the CORE

Generator wrappers. The sticky registers and management interface registers should not

be reset on DL_Down status or hot reset. The

LTSSM does not need to be reset, but it can be

reset after it transitions from Disabled (1011), Loopback (1001), Hot Reset (1010),

Recovery (1100), or Configuration (0011) to Detect (0001). This transition can be seen by

decoding the

L0LTSSMSTATE outputs of the integrated Endpoint block.

Table 2-2: The Effect of the RESETMODE Attribute on Reset Signal Functionality

Port RESETMODE

Reset Domain

user_cfg_rst mac_rst link_rst u_rst nv_rst mgmt_rst

CRMUSERCFGRSTN

FALSE •

CRMMACRSTN

(1)

FALSE

CRMLINKRSTN

(1)

FALSE

CRMURSTN

FALSE • • • •

CRMNVRSTN

FALSE • ••••

CRMMGMTRSTN

FALSE • •••••

CRMUSERCFGRSTN

TRUE •

CRMMACRSTN

TRUE •

CRMLINKRSTN

TRUE •

CRMURSTN

TRUE •

CRMNVRSTN

TRUE •

CRMMGMTRSTN

TRUE • • • • • •

Notes:

1. These ports are not used in this mode.