User guide

Virtex-5 FPGA Integrated Endpoint Block www.xilinx.com 23
UG197 (v1.5) July 22, 2009
Virtex-5 FPGA Integrated Endpoint Block Interface Descriptions
R
Resets
The integrated Endpoint block supports three types of resets, as defined by the PCI Express
Base Specification:
• Cold reset, a fundamental reset that occurs following the application of power.
• Warm reset, a fundamental reset that is triggered by hardware without the removal
and reapplication of power.
• Hot reset, an in-band mechanism for propagating reset across a PCIe link.
The registers in the integrated Endpoint block are divided into six reset domains:
• mgmt_rst: Management interface reset.
• nv_rst: Sticky (or non-volatile) registers reset. A sticky register retains its state through
a hot reset.
• user_cfg_rst: Endpoint Configuration Space reset. All registers in the Endpoint
Configuration Space, except the sticky registers, are affected.
• u_rst: Backend interface to the Transaction Layer (user_clk domain) reset.
• mac_rst: Physical Layer, including PL Lane reset.
• link_rst: Transaction Layer (core_clk domain), Data Link Layer, and part of the
Configuration and Capabilities module reset. This affects all registers in the block that
are not included in the other five reset domains.
There are six reset ports (see Table 2-3). The domain(s) that are reset by each port depend
on the
RESETMODE attribute (see Table 2-2).
• When
RESETMODE = FALSE, most of the ports reset more than one domain; thus,
only one of these signals should be asserted at a time. Two of the signals,
CRMMACRSTN and CRMLINKRSTN, are not used in this mode.
• When RESETMODE = TRUE, each port resets just one domain (except for
CRMMGMTRSTN, which resets the entire block); multiple reset signals can be asserted
as needed.
Figure 2-4: Clocking for Applications with CLKDIVIDED = FALSE
BUFG
GTP_DUAL
or
GTX_DUAL
Tile
core_clk (250 MHz)
CMT
PLL
User
Logic
Virtex-5 FPGA
Integrated
Endpoint Block
Retry
Block
RAMs
TX/RX
Block
RAMs
UG197_c2_10_081808
CRMCORECLK
CRMCORECLKRXO
CRMCORECLKTXO
CRMCORECLKDLO
CRMUSERCLK
CRMUSERCLKRXO
CRMUSERCLKTXO
BUFG
REFCLK
PLLLKDET
(100, 125, or 250 MHz)
REFCLK Frequency