User guide

20 www.xilinx.com Virtex-5 FPGA Integrated Endpoint Block
UG197 (v1.5) July 22, 2009
Chapter 2: Integrated Endpoint Block Functionality
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• Link initialization and training, including the Link Training and Status State Machine
(LTSSM)
• Generating scramble and descramble codes
Physical Layer Lane Module
There are eight Physical Layer lane modules, one for each lane that the integrated
Endpoint block supports.
On the transmission side of its operation, the PL lane module applies the scramble codes
generated by the Physical Layer module to the transmit data, multiplexes this with
ordered set data received from the Physical Layer module, and then passes the packet to
the transceiver interface for transmission.
On the receive side, the Physical Layer lane module receives TLP bytes from the
Transceiver interface, decodes ordered sets from this data, and descrambles DLLP and TLP
data from the resulting datastream.
This module also detects the receipt of electrical idle characters. The remaining Physical
Layer functionality, including lane-to-lane deskew and 8B/10B encoding and decoding, is
included in the RocketIO transceivers.
Configuration and Capabilities Module
The Configuration and Capabilities module principally provides the repository for the
different registers within the Configuration Space, including:
• Legacy PCI V3.0 Type 0 Configuration Space Header
• Legacy Capabilities
♦ PCI Express
♦ Power Management
♦ Message Signaled Interrupts (MSIs)
• PCI Express Extended Capabilities
♦ Device Serial Number
The integrated Endpoint block does not support the Advanced Error Reporting Capability.
The module also includes a packet decoder and a packet generator for handling
configuration and message packets.