User guide

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UG197 (v1.5) July 22, 2009

Architecture Overview

The PCI Express protocol supports four types of transactions: memory (read and write),

I/O (read and write), configuration (read and write), and message.

Transactions are divided into three categories: posted, non-posted, and completion

transactions. Memory writes and message transactions are posted transactions. The

requester sends a packet, but the receiver does not return a completion. Non-posted

transactions (memory reads, I/O reads and writes, and configuration reads and writes)

require a response and are implemented as split transactions.

Data Link Layer

The Data Link Layer (DLL) resides between the Transaction Layer and the Physical Layer.

Its primary responsibilities are link management and data integrity, including error

detection and correction.

The transmission portion of the DLL accepts TLPs from the Transaction Layer and

generates the appropriate TLP sequence number and Link CRC (LCRC), then passes the

packet to the Physical Layer. It also places a copy of the packet in a retry buffer, making it

available if the packet needs to be resent. Nullified packets are automatically purged from

the retry buffer.

The DLL also generates and consumes special packets called Data Link Layer packets

(DLLPs) that do not pass to the Transaction Layer. Types of DLLPs include

acknowledgment (ACK/NAK), flow control, and power management. When the DLL

detects errors in a packet, it requests retransmission of the packet until it is correctly

received or until the link is determined to have failed.

The reception portion of the DLL checks the integrity of received TLPs. It also orders

retransmission when the received TLP is found to be corrupt.

The reception portion of the DLL simply handles whatever is received, but the

transmission portion also controls the order of release of the different types of packets. A

prioritizer is included to sort the different sources of transmission into order of priority

and schedule them for transmission according to the priority order recommended in the

PCI Express Base 1.1 Specification.

Physical Layer

The Physical Layer module carries out the following functions:

• Packet framing and deframing

• Byte striping and unstriping; that is, distributing TX packets across multiple lanes and

reassembling RX packets received over multiple lanes

• Generation and reception of ordered sets

Figure 2-2: PCIe Protocol Packet

UG197_c2_02_071306

Start Header

Sequence

Number

ECRC

Presented to Transaction Layer

Appended by Data Link Layer

Appended by Physical Layer

EndLCRCData Payload