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18 www.xilinx.com Virtex-5 FPGA Integrated Endpoint Block

UG197 (v1.5) July 22, 2009

Chapter 2: Integrated Endpoint Block Functionality

Transaction Layer

The Transaction Layer (TL) is the upper layer in the architecture. It takes Transaction Layer

Packets (TLPs) presented by user logic at the Transaction Layer interface and schedules

them for transmission. The module also advises the user application when TLPs are

received.

TLPs can both make requests and complete requests from another device. They can also

communicate certain types of events.

A TLP is composed of a header, data payload (for most packets), and optional end-to-end

CRC (ECRC), as shown in Figure 2-2. The integrated Endpoint block does not support the

optional ECRC generation and checking; however, the block does pass through the ECRC

untouched.

The Transaction Layer also manages the credit-based flow control. The flow control

mechanism ensures that a packet is not transmitted unless the receiving device has

sufficient buffer space to accept it.

Figure 2-1: Virtex-5 FPGA Integrated Endpoint Block Diagram

Block

RAM

(TX)

Block

RAM

(RX)

Block

RAM

(Retry)

Block

RAM

Interface

Transaction

Layer

Transaction

Layer

Interface

Transceiver

Interface

Management

Interface

User

Application

Configuration and Capabilities Module

Miscellaneous Logic (Optional)

Clock and

Reset Block

Clock and

Reset Interface

Configuration and

tatus Interface

Physical

Layer

RocketIO

Transceiver(s)

Virtex-5 FPGA

Integrated

Endpoint Block

Data Link

Layer

PL Lane

Power

Management

Interface

UG197_c2_01_081908