User guide

Virtex-5 FPGA Integrated Endpoint Block www.xilinx.com 15

UG197 (v1.5) July 22, 2009

Memory Requirements

There are three buffers that require block RAM: the Retry buffer, the Receive (RX) buffer,

and the Transmit (TX) buffer. Each buffer has its own interface for independent access. The

amount of block RAM needed can vary greatly, depending on the user requirements. For

example, more block RAM is needed for the TX and RX buffers when there is a larger

maximum payload size. The amount of block RAM needed for the Retry buffer can

increase with multilane designs because the bandwidth is larger.

Table 1-2 shows the number of 36-kbit block RAM buffers required for several different

representative usages. The number varies from 3 to 40, depending on user requirements.

The typical column assumes a 128- or 256-byte maximum payload size. More information

on buffer sizing can be found in “Block RAM Interface,” page 40.

Use Models

The example topology shown in Figure 1-1 illustrates the major components in a PCIe

system. Endpoint blocks and Legacy Endpoint blocks, both upstream-facing ports, are

supported by the integrated Endpoint block.

Table 1-2: Number of 36-kbit Block RAMs Required

Number of 36-kbit Block RAMs

Minimum Typical Maximum

Receive Buffer 1 1 16

Transmit Buffer 1 1 16

Retry Buffer 1 1 8

Total 3 3 40

Figure 1-1: Topology of a PCIe System

UG197_c1_01_082008

Root Complex Memory

Virtex-5 FPGA

Legacy

Endpoint

Virtex-5 FPGA

Endpoint

Virtex-5 FPGA

Endpoint

Virtex-5 FPGA

Endpoint

Switch

Legend:

Upstream port

Downstream port

PCIe to

PCI

Bridge

CPU