User guide

120 www.xilinx.com Virtex-5 FPGA Integrated Endpoint Block
UG197 (v1.5) July 22, 2009
R
T
TLRAMREADLATENCY attribute 57, 98
TLRAMREADLATENCY port 32
TLRAMWRITELATENCY attribute 57, 98
TX buffer 15, 21, 25, 29, 35, 40, 41, 42, 91,
92, 98
TX Link 45
TXTSNFTS attribute 57, 98
TXTSNFTSCOMCLK attribute 57, 98
U
URREPORTINGENABLE port 52
V
VC0RXFIFOBASEC attribute 60, 91, 97
VC0RXFIFOBASENP attribute 60, 91, 97
VC0RXFIFOBASEP attribute 60, 91, 93,
97
VC0RXFIFOLIMITC attribute 60, 91, 93,
97
VC0RXFIFOLIMITNP attribute 60, 91, 97
VC0RXFIFOLIMITP attribute 60, 91, 93
VC0TOTALCREDITSCD attribute 60, 93,
96
VC0TOTALCREDITSCH attribute 60, 93,
96
VC0TOTALCREDITSNPH attribute 60, 93,
96
VC0TOTALCREDITSPD attribute 60, 93,
96
VC0TOTALCREDITSPH attribute 60, 93,
96
VC0TXFIFOBASEC attribute 61, 91, 96
VC0TXFIFOBASENP attribute 91, 96
VC0TXFIFOBASEP attribute 91, 92, 96
VC0TXFIFOLIMITC attribute 61, 91, 96
VC0TXFIFOLIMITNP attribute 61, 91, 96
VC0TXFIFOLIMITP attribute 61, 91, 92, 96
VCBASEPTR attribute 94, 95
VCCAPABILITYNEXTPTR attribute 95,
105
Vendor ID register 53
VENDORID attribute 38, 102
X
XPBASEPTR attribute 94, 95, 107
XPDEVICEPORTTYPE attribute 58, 102
XPMAXPAYLOAD attribute 41, 58, 94, 102