User guide

118 www.xilinx.com Virtex-5 FPGA Integrated Endpoint Block
UG197 (v1.5) July 22, 2009
R
L0MACRXL0SSTATE port 45
L0MSIENABLE0 port 50
L0MSIREQUEST0 bus 50
L0MULTIMSGEN0 bus 50
L0PACKETHEADERFROMUSER bus 52
L0PMEACK port 45
L0PMEEN port 45
L0PMEREQIN port 45
L0PMEREQOUT port 45
L0PWRL1STATE port 45
L0PWRL23READYSTATE port 45
L0PWRSTATE0 bus 45
L0PWRTURNOFFREQ port 45
L0PWRTXL0SSTATE port 45
L0RXDLLPM port 45
L0RXDLLPMTYPE bus 45
L0RXMACLINKERROR bus 46
L0SETCOMPLETERABORTERROR port
49
L0SETCOMPLETIONTIMEOUTCORRERR
OR
port 50
L0SETCOMPLETIONTIMEOUTUNCORRE
RROR
port 49
L0SETDETECTEDCORRERROR port 49
L0SETDETECTEDFATALERROR port 49
L0SETDETECTEDNONFATALERROR
port
49
L0SETUNEXPECTEDCOMPLETIONCOR
RERROR
port 50
L0SETUNEXPECTEDCOMPLETIONUNC
ORRERROR
port 50
L0SETUNSUPPORTEDREQUESTNONPO
STEDERROR
port 50
L0SETUNSUPPORTEDREQUESTOTHER
ERROR
port 50
L0SETUSERDETECTEDPARITYERROR
port
49
L0SETUSERMASTERDATAPARITY port
49
L0SETUSERRECEIVEDMASTERABORT
port
49
L0SETUSERRECEIVEDTARGETABORT
port
49
L0SETUSERSIGNALLEDTARGETABORT
port
49
L0SETUSERSYSTEMERROR port 49
L0SEXITLATENCY attribute 57, 98
L0SEXITLATENCYCOMCLK attribute 57,
99
L0STATSCFGOTHERRECEIVED port 51
L0STATSCFGOTHERTRANSMITTED port
51
L0STATSCFGRECEIVED port 51
L0STATSCFGTRANSMITTED port 51
L0STATSDLLPRECEIVED port 50
L0STATSDLLPTRANSMITTED port 50
L0STATSOSRECEIVED port 50
L0STATSOSTRANSMITTED port 50
L0STATSTLPRECEIVED port 50
L0STATSTLPTRANSMITTED port 51
L0TRANSACTIONSPENDING port 48
L0UNLOCKRECEIVED port 52
L1EXITLATENCY attribute 57, 99
L1EXITLATENCYCOMCLK attribute 57,
99
Link Capabilities register 55
Link Control register 55
LINKCAPABILITYASPMSUPPORT at-
tribute
104
LINKCAPABILITYMAXLINKWIDTH at-
tribute
77, 104
LINKSTATUSSLOTCLOCKCONFIG at-
tribute
105
LLKRXCHCOMPLETIONAVAILABLEN
bus
32, 37, 68
LLKRXCHFIFO bus 32, 36
LLKRXCHNONPOSTEDAVAILABLEN bus
32, 37, 68
LLKRXCHPOSTEDAVAILABLEN bus 32,
36, 68
LLKRXCHTC bus 32, 36
LLKRXCOMPLETIONAVAILABLEN bus
32
LLKRXDATA bus 32, 35
LLKRXDSTCONTREQN port 36
LLKRXDSTREQN port 32, 33, 36
LLKRXEOFN port 36
LLKRXNONPOSTEDAVAILABLEN bus 32
LLKRXPOSTEDAVAILABLEN bus 32
LLKRXPREFERREDTYPE bus 37, 67
LLKRXSOFN port 36
LLKRXSRCLASTREQN port 32, 33, 36
LLKRXSRCRDYN port 32, 36
LLKRXVALIDN bus 36
LLKTCSTATUS bus 34
LLKTXCHANSPACE bus 29, 35
LLKTXCHCOMPLETIONREADYN bus 29,
35
LLKTXCHFIFO bus 35
LLKTXCHNONPOSTEDREADYN bus 29,
35
LLKTXCHPOSTEDREADYN bus 29, 35
LLKTXCHTC bus 35
LLKTXCOMPLETIONREADYN bus 29, 35
LLKTXDATA bus 30, 34
LLKTXENABLEN bus 30, 35
LLKTXEOFN port 29, 30, 35
LLKTXNONPOSTEDREADYN bus 35
LLKTXPOSTEDREADYN bus 35
LLKTXSOFN port 29, 35
LLKTXSRCDSCN port 34
LOWPRIORITYVCCOUNT attribute 57,
102
M
Mask Bits register 55
MAXPAYLOADSIZE bus 51
MAXREADREQUESTSIZE bus 51
MEMSPACEENABLE port 51
Message Address register 55
Message Control register 55, 68
Message Data register 55
Message Upper Address register 55
MGMTADDR bus 37, 38
MGMTBWREN bus 38
MGMTPSO port 39
MGMTRDATA bus 37, 38
MGMTRDEN port 37, 38
MGMTSTATSCREDIT bus 39
MGMTSTATSCREDITSEL bus 39
MGMTWDATA bus 38
MGMTWREN port 38
MIMDLLBRADD bus 42
MIMDLLBRDATA bus 42
MIMDLLBREN port 42
MIMDLLBWADD bus 42
MIMDLLBWDATA bus 42
MIMDLLBWEN port 42
MIMRXBRADD bus 42
MIMRXBRDATA bus 42
MIMRXBREN port 42
MIMRXBWADD bus 42
MIMRXBWDATA bus 42
MIMRXBWEN port 42
MIMTXBRADD bus 42
MIMTXBRDATA bus 42
MIMTXBREN port 42
MIMTXBWADD bus 42
MIMTXBWDATA bus 42
MIMTXBWEB port 42
MSIBASEPTR attribute 94, 95, 107
MSICAPABILITYMULTIMSGCAP at-
tribute
104
MSICAPABILITYNEXTPTR attribute 95,
103
N
Next Cap Pointer register 55
Next Capability Pointer register 54