User guide

Virtex-5 FPGA Integrated Endpoint Block www.xilinx.com 117
UG197 (v1.5) July 22, 2009
A
ACTIVELANESIN attribute 24, 58, 77, 98
AERBASEPTR attribute 94, 95
AERCAPABILITYNEXTPTR attribute 95,
105
AUXPOWER port 52
B
BAR0 register 53
BAR0ADDRWIDTH attribute 59, 99
BAR0EXIST attribute 59, 99
BAR0IOMEMN attribute 58, 101
BAR0MASKWIDTH attribute 58, 101
BAR0PREFETCHABLE attribute 58, 100
BAR1 register 53
BAR1ADDRWIDTH attribute 59, 100
BAR1EXIST attribute 59, 99
BAR1IOMEMN attribute 58, 101
BAR1MASKWIDTH attribute 58, 101
BAR1PREFETCHABLE attribute 58, 100
BAR2 register 53
BAR2ADDRWIDTH attribute 59, 100
BAR2EXIST attribute 59, 99
BAR2IOMEMN attribute 58, 101
BAR2MASKWIDTH attribute 58, 101
BAR2PREFETCHABLE attribute 58, 100
BAR3 register 53
BAR3ADDRWIDTH attribute 59, 100
BAR3EXIST attribute 59, 99
BAR3IOMEMN attribute 58, 101
BAR3MASKWIDTH attribute 58, 101
BAR3PREFETCHABLE attribute 58, 100
BAR4 register 53
BAR4ADDRWIDTH attribute 59, 100
BAR4EXIST attribute 59, 99
BAR4IOMEMN attribute 58, 101
BAR4MASKWIDTH attribute 58, 101
BAR4PREFETCHABLE attribute 58, 100
BAR5 register 53
BAR5EXIST attribute 59, 99
BAR5IOMEMN attribute 58, 101
BAR5MASKWIDTH attribute 58, 101
BAR5PREFETCHABLE attribute 58, 101
base_addr0_mask register 53
base_addr1_mask register 53
base_addr2_mask register 53
base_addr3_mask register 53
base_addr4_mask register 53
base_addr5_mask register 53
buffer capacity 41
buffer latency 92
buffer layout 91
BUSMASTERENABLE port 52
C
Cache Line Size register 53
CAPABILITIESPOINTER attribute 94, 95,
102
Capability ID register 54, 55
Cardbus CIS Pointer register 53
CARDBUSCISPOINTER attribute 102
Class Code register 53
CLASSCODE attribute 102
CLKDIVIDED attribute 106
command register 53
COMPLIANCEAVOID port 46
CRMCORECLK port 21, 25
CRMCORECLKDLLO port 21
CRMCORECLKDLO port 25
CRMCORECLKRXO port 21, 25
CRMCORECLKTXO port 21, 25
CRMDOHOTRESETN port 27
CRMLINKRSTN port 24
CRMMACRSTN port 24
CRMMGMTRSTN port 24, 38
CRMNVRSTN port 24, 26, 38
CRMPWRSOFTRESETN port 27
CRMURSTN port 24, 38
CRMUSERCFGRSTN port 24, 26
CRMUSERCLK port 25, 37, 38, 51
CRMUSERCLKRXO port 21, 25
D
Device Capabilities register 55
Device Control register 55
Device ID register 53
Device Status register 55
DEVICECAPABILITYENDPOINTL0SLATE
NCY
attribute 104
DEVICECAPABILITYENDPOINTL1LATEN
CY
attribute 104
DEVICEID attribute 37, 38, 102
DEVICESERIALNUMBER attribute 105
DLLTXPMDLLPOUTSTANDING port 52
DSNBASEPTR attribute 94, 95, 107
DSNCAPABILITYNEXTPTR attribute 95,
105
E
Endpoint Cap ID register 55
Endpoint Capabilities register 55
Endpoint Enhanced Capability Header
register
56
Expansion ROM Base Address register
53
H
Header Type register 53
I
INFINITECOMPLETIONS attribute 58, 93,
94, 98
Interrupt Line register 53
Interrupt Pin register 53
INTERRUPTDISABLE port 52, 69
INTERRUPTPIN attribute 102
IOSPACEENABLE port 51
L
L0CFGDISABLESCRAMBLE port 48
L0CFGLOOPBACKACK port 46
L0CFGLOOPBACKMASTER port 46, 48
L0COMPLETERID bus 48
L0DLLERRORVECTOR bus 48
L0DLLRXACKOUTSTANDING port 45
L0DLLTXNONFCOUTSTANDING port 45
L0DLLTXOUTSTANDING port 45
L0DLLVCSTATUS bus 47
L0DLUPDOWN bus 48
L0FIRSTCFGWRITEOCCURRED port 46
L0LEGACYINTFUNCT0 port 50
L0LTSSMSTATE bus 47
L0MACENTEREDL0 port 45
L0MACLINKTRAINING port 47
L0MACLINKUP port 46
L0MACNEGOTIATEDLINKWIDTH bus 47,
77
L0MACNEWSTATEACK port 45
Index