User guide

116 www.xilinx.com Virtex-5 FPGA Integrated Endpoint Block
UG197 (v1.5) July 22, 2009
R
multiple virtual channels. There is no correspondence between the
number of virtual channels and the number of Lanes.
W
X
x1, x2, x4, x8, etc.
A notation for designating how many lanes are included in the PCI
Express link (1, 2, 4, 8 in this example). Pronounced by 1, by 2, by 4,
by 8, etc.
Y
Z