User guide

Virtex-5 FPGA Integrated Endpoint Block www.xilinx.com 113
UG197 (v1.5) July 22, 2009
R
L
Lane
A set of differentially driven signal lines, one for each direction of data
flow. A 1-lane PCI Express implementation is sometimes referred to as
“x1” (by-1), a 4-lane implementation “x4” (by-4), and so on.
LCRC
Link CRC. A CRC added by the Data Link Layer, that covers the entire
TLP and the sequence number. It is checked by the neighboring
receiver device.
Legacy Interrupt
PCI interrupt delivery using active Low INTA signal.
Link
A communication path between two PCI Express components. A link
consists of one or more lanes.
M
MRd32
Memory Read Request (32-bit).
MRd64
Memory Read Request (64-bit).
MWr32
Memory Write Request (32-bit).
MWr64
Memory Write Request (64-bit).
MSI
Message Signaled Interrupt.
N