User guide

Virtex-5 FPGA Integrated Endpoint Block www.xilinx.com 111
UG197 (v1.5) July 22, 2009
R
D
Data Link Layer
The middle layer of the PCI Express architecture, that is between the
Transaction Layer and the Physical Layer. See “Data Link Layer” on
page 19.
Digest
A single 32-bit DW at the end of a TLP, containing an ECRC value.
DL_Down
DL_Down status indicates that there is no connection with another
component on the Link, or that the connection with the other
component has been lost and is not recoverable by the Physical or
Data Link Layer.
DLLP
Data Link Layer Packet. A packet generated in the Data Link Layer to
support Link management functions.
DSN
Device Serial Number.
DWORD, DW
Four bytes.
E
ECRC
End-to-end CRC. The ECRC is generated by the source component on
the header and data of the TLP and checked by the ultimate
destination component. A switch forwards the ECRC untouched,
unless the packet is destined for the switch itself. ECRC is optional,
and requires Advanced Error Reporting support.
F
Flow control
The protocol that determines how transactions flow between the
various ports in a PCI Express fabric. It is a method for communicating
receive buffer status from a receiver to a transmitter to prevent receive
buffer overflow and allow transmitter compliance with ordering rules.