User guide

106 www.xilinx.com Virtex-5 FPGA Integrated Endpoint Block
UG197 (v1.5) July 22, 2009
Appendix A: Integrated Endpoint Block Attributes
R
PBCAPABILITYDW0DATASCALE
2-bit Hex Reserved. Must be set to 0h.
PBCAPABILITYDW0PMSUBSTATE
3-bit Hex Reserved. Must be set to 0h.
PBCAPABILITYDW0PMSTATE
2-bit Hex Reserved. Must be set to 0h.
PBCAPABILITYDW0TYPE
3-bit Hex Reserved. Must be set to 0h.
PBCAPABILITYDW0POWERRAIL
3-bit Hex Reserved. Must be set to 0h.
PBCAPABILITYDW1BASEPOWER
8-bit Hex Reserved. Must be set to 0h.
PBCAPABILITYDW1DATASCALE
2-bit Hex Reserved. Must be set to 0h.
PBCAPABILITYDW1PMSUBSTATE
3-bit Hex Reserved. Must be set to 0h.
PBCAPABILITYDW1PMSTATE
2-bit Hex Reserved. Must be set to 0h.
PBCAPABILITYDW1TYPE
3-bit Hex Reserved. Must be set to 0h.
PBCAPABILITYDW1POWERRAIL
3-bit Hex Reserved. Must be set to 0h.
PBCAPABILITYDW2BASEPOWER
8-bit Hex Reserved. Must be set to 0h.
PBCAPABILITYDW2DATASCALE
2-bit Hex Reserved. Must be set to 0h.
PBCAPABILITYDW2PMSUBSTATE
3-bit Hex Reserved. Must be set to 0h.
PBCAPABILITYDW2PMSTATE
2-bit Hex Reserved. Must be set to 0h.
PBCAPABILITYDW2TYPE
3-bit Hex Reserved. Must be set to 0h.
PBCAPABILITYDW2POWERRAIL
3-bit Hex Reserved. Must be set to 0h.
PBCAPABILITYDW3BASEPOWER
8-bit Hex Reserved. Must be set to 0h.
PBCAPABILITYDW3DATASCALE
2-bit Hex Reserved. Must be set to 0h.
PBCAPABILITYDW3PMSUBSTATE
3-bit Hex Reserved. Must be set to 0h.
PBCAPABILITYDW3PMSTATE
2-bit Hex Reserved. Must be set to 0h.
PBCAPABILITYDW3TYPE
3-bit Hex Reserved. Must be set to 0h.
PBCAPABILITYDW3POWERRAIL
3-bit Hex Reserved. Must be set to 0h.
PBCAPABILITYSYSTEMALLOCATED
Boolean Reserved. Must be set to FALSE.
RESETMODE
Boolean A value of FALSE selects a hierarchical reset scheme
that uses four reset domains. A value of TRUE
selects a 6-domain reset scheme where each signal
resets a separate domain, except for
CRMMGMTRSTN, which resets the entire block for
either
RESETMODE setting. See Table 2-3, page 25
for more information.
CLKDIVIDED
Boolean Specifies whether the user_clk domain frequency is
a divided version of the core_clk domain frequency.
Set to FALSE when user_clk frequency is the same as
core_clk.
Set to TRUE when the user_clk frequency is one half
or one quarter the frequency of the core_clk.
Table A-7: Integrated Endpoint Block Attributes (Continued)
Attribute Name Type Description