User guide

Virtex-5 FPGA Integrated Endpoint Block www.xilinx.com 105
UG197 (v1.5) July 22, 2009
Integrated Endpoint Block Attributes
R
LINKSTATUSSLOTCLOCKCONFIG
Boolean Slot Clock Configuration. Indicates where the
component uses the same physical reference clock
that the platform provides on the connector. For a
port that connects to the slot, indicates that it uses a
clock with a common source to that used by the slot.
For an adaptor inserted in the slot, indicates that it
uses the same clock source as the slot, not a locally-
derived clock source.
Transferred to the Link Status register (see
Table 2-20, page 55).
AERCAPABILITYNEXTPTR
12-bit Hex Next Capability Offset. The offset to the next PCI
Express capability structure or 000h if no further
capability structures are available at higher
addresses.
Should be set to
PBBASEPTR.
VCCAPABILITYNEXTPTR
12-bit Hex Next Capability Offset. The offset to the next PCI
Express capability structure or 000h if no further
capability structures are available at higher
addresses.
Must be set to 000h.
PORTVCCAPABILITYEXTENDEDVCCOUNT
3-bit Hex Extended VC Count. Indicates the number of
(extended) VCs in addition to the default VC
supported by the device. Should be set to 0.
PORTVCCAPABILITYVCARBCAP
8-bit Hex VC Arbitration Capability. Indicates the types of VC
Arbitration supported for VCs in the LPVC group.
Should be set to 0h.
PORTVCCAPABILITYVCARBTABLEOFFSET
8-bit Hex VC Arbitration Table Offset. Contains the offset of
the base of the VC Arbitration Table from the base
address of the VC Capability structure, expressed in
DQWords (16 bytes). Should be set to 0h.
DSNCAPABILITYNEXTPTR
12-bit Hex Next Capability Offset. The offset to the next PCI
Express capability structure above DSN (Device
Serial Number) or 000h if no further capability
structures are available at higher addresses.
DEVICESERIALNUMBER
64-bit Hex PCI Express Device Serial Number. IEEE-defined
EUI-64 64-bit extended unique identifier. This
identifier includes a 24-bit company ID value
assigned by IEEE registration authority and a 40-bit
extension assigned by the manufacturer to identify
the particular device.
PBCAPABILITYNEXTPTR
12-bit Hex Next Capability Offset. The offset to the next PCI
Express capability structure above power budgeting
or 000h if no further capability structures are
available at higher addresses.
Should be set to
DSNBASEPTR.
PBCAPABILITYDW0BASEPOWER
8-bit Hex Reserved. Must be set to 0h.
Table A-7: Integrated Endpoint Block Attributes (Continued)
Attribute Name Type Description