User guide

104 www.xilinx.com Virtex-5 FPGA Integrated Endpoint Block
UG197 (v1.5) July 22, 2009
Appendix A: Integrated Endpoint Block Attributes
R
MSICAPABILITYMULTIMSGCAP
3-bit Hex Multiple Message Capable. Each MSI function can
request up to four unique messages. System
software can read this field to determine the number
of messages requested. Number of messages
requested are encoded as follows:
0h: 1
1h: 2
2h: 4
PCIECAPABILITYNEXTPTR
8-bit Hex The offset to the next PCI Capability Structure or
00h if no further capability structures are available
at higher addresses.
Must be set to 0h.
DEVICECAPABILITYENDPOINTL0SLATENCY
3-bit Hex Endpoint L0s Acceptable Latency. Records the
latency the Endpoint can withstand on transitions
from the L0s state to L0. Valid settings are:
0h: Maximum of 64 ns
1h: Maximum of 128 ns
2h: Maximum of 256 ns
3h: Maximum of 512 ns
4h: Maximum of 1 µs
5h: Maximum of 2 µs
6h: Maximum of 4 µs
7h: No limit
DEVICECAPABILITYENDPOINTL1LATENCY
3-bit Hex Endpoint L1 Acceptable Latency. Records the
latency that the Endpoint can withstand on
transitions from the L1 state to L0 (if the L1 state is
supported). Valid settings are:
0h: Maximum of 1 µs
1h: Maximum of 2 µs
2h: Maximum of 4 µs
3h: Maximum of 8 µs
4h: Maximum of 16 µs
5h: Maximum of 32 µs
6h: Maximum of 64 µs
7h: No limit
LINKCAPABILITYMAXLINKWIDTH
6-bit Hex Maximum Link Width. Valid settings are:
1h: x1
2h: x2
4h: x4
8h: x8
LINKCAPABILITYASPMSUPPORT
2-bit Hex Active State PM Support. Indicates the level of
active state power management supported by the
selected PCI Express Link, encoded as follows:
0h: Reserved
1h: L0s entry supported
2h: Reserved
3h: L0s and L1 entry supported
Must be set to 1h.
Table A-7: Integrated Endpoint Block Attributes (Continued)
Attribute Name Type Description