User guide

102 www.xilinx.com Virtex-5 FPGA Integrated Endpoint Block
UG197 (v1.5) July 22, 2009
Appendix A: Integrated Endpoint Block Attributes
R
XPDEVICEPORTTYPE
4-bit Hex Identifies the type of device/port as follows:
0h: Endpoint device for PCI Express designs
1h: Legacy Endpoint device for PCI Express
designs
Transferred to PCI Express Capabilities register (see
Table 2-20, page 55).
XPMAXPAYLOAD
Integer Specifies maximum payload supported. Valid
settings are:
0: 128 bytes
1: 256 bytes
2: 512 bytes
3: 1024 bytes
4: 2048 bytes
5: 4096 bytes
Transferred to the Device Capabilities register.
LOWPRIORITYVCCOUNT
Integer Sets the number of VCs in addition to VC0 that are
to be included in the Low Priority VC group.
Should be set to 0.
VENDORID
16-bit Hex Unique Manufacturer ID. Transferred to the Vendor
ID register.
DEVICEID
16-bit Hex Unique Device ID. Transferred to the Device ID
register.
REVISIONID
8-bit Hex ID identifying revision of device. Transferred to the
Revision ID register.
CLASSCODE
24-bit Hex Code identifying basic function, subclass and
applicable programming interface. Transferred to
the Class Code register.
CARDBUSCISPOINTER
32-bit Hex Pointer to Cardbus data structure. Transferred to the
Cardbus CIS Pointer register.
SUBSYSTEMVENDORID
16-bit Hex ID that can be used to provide additional vendor
information to that provided by Vendor ID.
Transferred to the Subsystem Vendor ID register.
SUBSYSTEMID
16-bit Hex ID that can be used to provide additional device
information to that provided by Device ID.
Transferred to the Subsystem ID register.
CAPABILITIESPOINTER
8-bit Hex Points to the first capabilities structure
INTERRUPTPIN
8-bit Hex Indicates mapping for legacy interrupt messages.
Valid values are:
0h: No legacy interrupt messages used.
1h: INTA
PMCAPABILITYNEXTPTR
8-bit Hex The offset to the next PCI Capability Structure or
00h if no further capability structures are available
at higher addresses.
Table A-7: Integrated Endpoint Block Attributes (Continued)
Attribute Name Type Description