User guide

10 www.xilinx.com Virtex-5 FPGA Integrated Endpoint Block
UG197 (v1.5) July 22, 2009
Preface: About This Guide
R
attributes are all set through the CORE Generator GUI, this appendix is provided as a
reference.
• “Glossary,” defines various terms used in this document.
Additional Documentation
The following documents are also available for download at
http://www.xilinx.com/virtex5
.
• Virtex-5 Family Overview
The features and product selection of the Virtex-5 family are outlined in this overview.
• Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
This data sheet contains the DC and Switching Characteristic specifications for the
Virtex-5 family.
• Virtex-5 FPGA User Guide
Chapters in this guide cover the following topics:
- Clocking Resources
- Clock Management Technology (CMT)
- Phase-Locked Loops (PLLs)
-Block RAM
- Configurable Logic Blocks (CLBs)
-SelectIO™ Resources
- SelectIO Logic Resources
- Advanced SelectIO Logic Resources
• Virtex-5 FPGA RocketIO GTP Transceiver User Guide
This guide describes the RocketIO™ GTP transceivers available in the Virtex-5 LXT
and SXT devices.
• Virtex-5 FPGA RocketIO GTX Transceiver User Guide
This guide describes the RocketIO GTX transceivers available in the TXT and FXT
devices.
• Virtex-5 FPGA Embedded Processor Block in Virtex-5 FPGAs
This reference guide is a description of the embedded processor block available in the
Virtex-5 FXT device.
• Virtex-5 FPGA Embedded Tri-Mode Ethernet MAC User Guide
This guide describes the dedicated Tri-Mode Ethernet Media Access Controller
available in the Virtex-5 LXT, SXT, TXT, and FXT devices.
• Virtex-5 FPGA XtremeDSP Design Considerations User Guide
This guide describes the XtremeDSP™ slice and includes reference designs for using
the DSP48E.
• Virtex-5 FPGA Configuration Guide
This all-encompassing configuration guide includes chapters on configuration
interfaces (serial and SelectMAP), bitstream encryption, Boundary-Scan and JTAG
configuration, reconfiguration techniques, and readback through the SelectMAP and
JTAG interfaces.