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Virtex-5 FPGA

Integrated Endpoint Block

for PCI Express Designs

User Guide

UG197 (v1.5) July 22, 2009

Summary of content (120 pages)

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Virtex-5 FPGA Integrated Endpoint Block for PCI Express Designs User Guide UG197 (v1.
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R Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit the Documentation in any form or by any means including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise, without the prior written consent of Xilinx.
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Revision History The following table shows the revision history for this document. Date Version Revision 09/06/06 1.0 Initial Xilinx release on CD. 03/20/07 1.1 Moved “TX and RX Buffer Layout” and “Buffer Latency” from Chapter 2 to Appendix A. Renamed Chapter 3 to “Designing with the Endpoint Block Plus Wrapper”and replaced content. Split Error Reporting table into Table 4-3 (PCIe Block action) and Table 4-4 (User action). Added VHDL code examples to “Simulating in VHDL” in Chapter 5. 12/13/07 1.
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Date Version Revision 09/23/08 1.4 • Removed references to Virtual Channel 1 (VC1) and multiple VCs throughout the document. • Changed references to RocketIO GTP transceiver to RocketIO transceiver to include GTX transceivers as well. • Changed references to CORE Generator Wrapper to Endpoint Block Plus Wrapper. • Rewrote introduction to “About This Guide,” page 9. • Added “Additional Documentation,” page 10.
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Table of Contents Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Preface: About This Guide Guide Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Additional Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Additional Support Resources . . . . . . . . . . . . . .
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R Configuration and Status Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Legacy Configuration Registers (Type 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Management Capability Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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R ACK Ignored When Followed by IDLE Ordered Set . . . . . . . . . . . . . . . . . . . . . . . . . . . Workaround . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Access to Unimplemented Configuration Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Workaround . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Receive TLPs with Illegal Payload Length . . . .
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R 8 www.xilinx.com Virtex-5 FPGA Integrated Endpoint Block UG197 (v1.
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R Preface About This Guide This guide serves as a technical reference describing the Virtex®-5 FPGA Integrated Endpoint Block for PCI Express® designs (integrated Endpoint block). Users intending to implement the integrated Endpoint block should use the CORE Generator™ tool to create the LogiCORE™ IP Endpoint Block Plus for PCI Express (Endpoint Block Plus wrapper). The Endpoint Block Plus wrapper contains all the settings and interface logic needed to create a compliant PCI Express design.
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R Preface: About This Guide attributes are all set through the CORE Generator GUI, this appendix is provided as a reference. • “Glossary,” defines various terms used in this document. Additional Documentation The following documents are also available for download at http://www.xilinx.com/virtex5. • Virtex-5 Family Overview The features and product selection of the Virtex-5 family are outlined in this overview.
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R Additional Support Resources • Virtex-5 FPGA System Monitor User Guide The System Monitor functionality available in all the Virtex-5 devices is outlined in this guide. • Virtex-5 FPGA Packaging and Pinout Specifications This specification includes the tables for device/package combinations and maximum I/Os, pin definitions, pinout tables, pinout diagrams, mechanical drawings, and thermal specifications.
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R Preface: About This Guide 12 www.xilinx.com Virtex-5 FPGA Integrated Endpoint Block UG197 (v1.
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R Chapter 1 Virtex-5 FPGA Integrated Endpoint Block Overview Summary This chapter introduces the integrated Endpoint block embedded in Virtex-5 devices. The sections include: • “The PCI Express Standard” • “Virtex-5 FPGA Integrated Endpoint Block for PCI Express Designs” • “Memory Requirements” • “Use Models” The PCI Express Standard The PCI Express (PCIe®) standard is a next-generation evolution of the older PCI™ and PCI-X™ parallel bus standards.
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R Chapter 1: Virtex-5 FPGA Integrated Endpoint Block Overview Virtex-5 FPGA Integrated Endpoint Block for PCI Express Designs The Virtex-5 FPGA Integrated Endpoint block contains the functionality defined in the specifications maintained by the PCI-SIG (www.pcisig.com): • Compliant with the PCI Express Base 1.
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R Memory Requirements Memory Requirements There are three buffers that require block RAM: the Retry buffer, the Receive (RX) buffer, and the Transmit (TX) buffer. Each buffer has its own interface for independent access. The amount of block RAM needed can vary greatly, depending on the user requirements. For example, more block RAM is needed for the TX and RX buffers when there is a larger maximum payload size.
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Chapter 1: Virtex-5 FPGA Integrated Endpoint Block Overview 16 www.xilinx.com R Virtex-5 FPGA Integrated Endpoint Block UG197 (v1.
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R Chapter 2 Integrated Endpoint Block Functionality Summary This chapter presents information on the architecture and functionality of the Virtex-5 FPGA Integrated Endpoint block. The sections include: • “Architecture Overview” • “Virtex-5 FPGA Integrated Endpoint Block Interface Descriptions” • “Registers” Architecture Overview The PCI Express protocol is divided into three layers: the Transaction Layer, the Data Link Layer, and the Physical Layer.
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R Chapter 2: Integrated Endpoint Block Functionality Block RAM (TX) Block RAM (RX) Block RAM (Retry) Block RAM Interface PL Lane Transaction Layer Interface PL Lane PL Lane Transaction Layer Data Link Layer Physical Layer Transceiver Interface PL Lane PL Lane RocketIO Transceiver(s) PL Lane PL Lane PL Lane User Application Management Interface Configuration and Capabilities Module Power Management Interface Configuration and Status Interface Miscellaneous Logic (Optional) Virtex-5 FPGA Inte
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R Architecture Overview The PCI Express protocol supports four types of transactions: memory (read and write), I/O (read and write), configuration (read and write), and message. Transactions are divided into three categories: posted, non-posted, and completion transactions. Memory writes and message transactions are posted transactions. The requester sends a packet, but the receiver does not return a completion.
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R Chapter 2: Integrated Endpoint Block Functionality • Link initialization and training, including the Link Training and Status State Machine (LTSSM) • Generating scramble and descramble codes Physical Layer Lane Module There are eight Physical Layer lane modules, one for each lane that the integrated Endpoint block supports.
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R Virtex-5 FPGA Integrated Endpoint Block Interface Descriptions Virtex-5 FPGA Integrated Endpoint Block Interface Descriptions The following subsections describe the physical interfaces on the integrated Endpoint block. Connections and control of these interfaces are contained within the Endpoint Block Plus Wrapper for PCI Express available from the CORE Generator GUI. The Endpoint Block Plus Wrapper for PCI Express uses the integrated Endpoint block to create a PCI Express Endpoint in the Virtex-5 FPGA.
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R Chapter 2: Integrated Endpoint Block Functionality Table 2-1: Clock Frequency Versus Lane Width (Continued) Configured Lane Width core_clk Frequency (MHz) user_clk Frequency (MHz)(1) x4 250 125 or 250 x8 250 250 Notes: 1. The user_clk frequency is based on the configured lane width. It cannot be reduced, even when the negotiated lane width is smaller. When the frequency of the user_clk domain is 250 MHz, there is no need to provide two separate clocks to the integrated Endpoint block.
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R Virtex-5 FPGA Integrated Endpoint Block Interface Descriptions CRMCORECLK CRMCORECLKRXO CRMCORECLKTXO CRMCORECLKDLO BUFG PLLLKDET CMT PLL BUFG CRMUSERCLK CRMUSERCLKRXO CRMUSERCLKTXO Virtex-5 FPGA Integrated Endpoint Block REFCLK Frequency REFCLK (100, 125, or 250 MHz) GTP_DUAL or GTX_DUAL Tile TX/RX Block RAMs Retry Block RAMs User Logic core_clk (250 MHz) UG197_c2_10_081808 Figure 2-4: Clocking for Applications with CLKDIVIDED = FALSE Resets The integrated Endpoint block supports three ty
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R Chapter 2: Integrated Endpoint Block Functionality Table 2-2: The Effect of the RESETMODE Attribute on Reset Signal Functionality Reset Domain Port RESETMODE user_cfg_rst mac_rst link_rst u_rst nv_rst CRMUSERCFGRSTN FALSE CRMMACRSTN(1) FALSE CRMLINKRSTN(1) FALSE CRMURSTN FALSE • • • • CRMNVRSTN FALSE • • • • • CRMMGMTRSTN FALSE • • • • • CRMUSERCFGRSTN TRUE • CRMMACRSTN TRUE CRMLINKRSTN TRUE CRMURSTN TRUE CRMNVRSTN TRUE CRMMGMTRSTN TRUE mgmt_rst • • • •
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R Virtex-5 FPGA Integrated Endpoint Block Interface Descriptions The CRMPWRSOFTRESETN output indicates when the integrated Endpoint block transitions from the D3hot power state to the D0uninitialized state. This transition must be used to trigger the assertion of the CRMUSERCFGRSTN port on the integrated Endpoint block. This is done in the CORE Generator wrappers. Ports Table 2-3 shows the Clock and Reset interface ports.
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R Chapter 2: Integrated Endpoint Block Functionality Table 2-3: Clock and Reset Ports (Continued) Direction Clock Domain CRMURSTN Input core_clk User reset (active Low). When the RESETMODE attribute is set to FALSE, resets all the registers in the integrated Endpoint block, except the sticky registers and the Management Interface registers. When the RESETMODE attribute is set to TRUE, resets the backend interface to the Transaction Layer (user_clk domain).
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R Table 2-3: Virtex-5 FPGA Integrated Endpoint Block Interface Descriptions Clock and Reset Ports (Continued) Direction Clock Domain CRMDOHOTRESETN Output core_clk Hot reset (active Low). Asserted on completion of hot reset handshake as a prompt for user logic to be reset. See “Resets,” page 23. CRMPWRSOFTRESETN Output core_clk Soft reset (active Low). Asserted when the block makes the transition from D3hot to D0uninitialized, as a prompt for user logic to be reset (with CRMUSERCFGRSTN).
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R Chapter 2: Integrated Endpoint Block Functionality Transaction Layer Interface Packets are presented to and received from the integrated Endpoint block’s Transaction Layer through the Transaction Layer interface. On this interface, a beat is a clock cycle where both the source and destination are ready. The main Transaction Layer interface framing signals indicate the start of frame, the end of frame, destination ready, and source ready.
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R Virtex-5 FPGA Integrated Endpoint Block Interface Descriptions CRMUSERCLK LLKTXSOFN LLKTXEOFN LLKTXSRCRDYN LLKTXDSTRDYN LLKTXDATA LLKTXENABLEN H0 H1 H2 H3 00 00 P0 P1 00 P2 P3 00 00 11 P4 P5 P6 P7 00 00 11 11 UG197_c2_03_111906 Figure 2-5: Transaction Layer Interface Transmit Timing Diagram Showing a 4 DW Header Channels The Transaction Layer interface allows for the generic concept of channels to deal with multiple logical channels for one physical interface.
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R Chapter 2: Integrated Endpoint Block Functionality Framing Errors The following conditions are framing errors and are not allowed: • Two SOFs without an intervening EOF • Two EOFs without an intervening SOF • An SOF and EOF in the same cycle DWORD Enables The Transaction Layer interface data bus, LLKTXDATA, is 64 bits wide, allowing the user to transfer one QWORD of data into the integrated Endpoint block per clock cycle.
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R Virtex-5 FPGA Integrated Endpoint Block Interface Descriptions Note: Need to wait an additional two cycles of LLKTXDSTRDYN assertion after LLKTXEOFN before switching LLKTXCHFIFO or LLKTXCHTC.
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R Chapter 2: Integrated Endpoint Block Functionality Receive Framing The receive framing signals are similar to the transmit framing signals. In receive packets, the header is always before the data. LLKRXVALIDN = 00 on all valid cycles except the last one. If the total number of 32-bit DWORDs (header plus payload) is odd, LLKRXVALIDN is 01 on the last beat.
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R Virtex-5 FPGA Integrated Endpoint Block Interface Descriptions When there is no more data to receive, LLKRXDSTREQN must be deasserted in the cycle after LLKRXSRCLASTREQN is first asserted. See Figure 2-7. Failure to do this causes the block to enter an undefined state; as a result, subsequent packets can be corrupted.
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R Chapter 2: Integrated Endpoint Block Functionality If LLKRXDSTREQN is deasserted in each of the three cycles, including initial assertion of LLKRXSRCLASTREQN, then one more request is required to complete reception of the current packet. To complete reception, the user must assert LLKRXDSTREQN for one subsequent cycle. See Figure 2-8. LLKRXSRCLASTREQN remains asserted until three cycles after the integrated Endpoint block has received the final request for the current RX packet.
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R Table 2-6: Virtex-5 FPGA Integrated Endpoint Block Interface Descriptions Transaction Layer Interface Ports (Continued) Port LLKTXCHANSPACE[9:0] Direction Clock Domain Output user_clk Description Amount of free space in the TX FIFO as selected by LLKTXCHTC and LLKTXCHFIFO.
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R Chapter 2: Integrated Endpoint Block Functionality Table 2-6: Transaction Layer Interface Ports (Continued) Direction Clock Domain LLKRXSRCRDYN Output user_clk LLKRXDSTREQN Input user_clk Port Description Asserted (active Low) for one cycle if the receive source has data available on LLKRXDATA in response to an earlier LLKRXDSTREQN. Data must be captured by the user design during the cycle LLKRXSRCRDYN is asserted. LLKRXSRCRDYN reflects the value of LLKRXVALID[1:0].
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R Table 2-6: Virtex-5 FPGA Integrated Endpoint Block Interface Descriptions Transaction Layer Interface Ports (Continued) Port Direction Clock Domain LLKRXCHNONPOSTEDAVAILABLEN[7:0] Output user_clk Traffic classes with complete non-posted packets available (active Low). LLKRXCHCOMPLETIONAVAILABLEN[7:0] Output user_clk Traffic classes with complete completion packets available (active Low).
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R Chapter 2: Integrated Endpoint Block Functionality performing the final Management write to the attribute address. This must be done to allow the new values to propagate within the integrated Endpoint block. The reset port(s) should be asserted for an additional four CRMUSERCLK cycles after the final assertion of MGMTWREN (see Figure 2-10). The exact port(s) that must be asserted to reset the block (indicated by “reset” in the timing diagram) depends on the reset mode.
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R Table 2-7: Virtex-5 FPGA Integrated Endpoint Block Interface Descriptions Management Interface Ports (Continued) Port MGMTSTATSCREDIT[11:0] Direction Clock Domain Output user_clk Description Credit information as selected by MGMTSTATSCREDITSEL[6:0]. MGMTSTATSCREDIT[11:0] is updated two cycles after MGMTSTATSCREDITSEL[6:0] is switched. MGMTSTATSCREDITSEL[6:0] Input user_clk Channel select for credit information output to MGMTSTATSCREDIT[11:0].
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R Chapter 2: Integrated Endpoint Block Functionality Block RAM Interface The Transmit (TX), Receive (RX), and Retry buffers are implemented with block RAM. Each buffer has separate read and write interfaces. The sizes of the buffers can vary based on the application’s needs. • Transmit buffer. Buffers transmitted packets. It is divided into separate FIFOs for posted, non-posted, and completion transactions (see Figure A-1, page 91 and Table A-7, page 96). • Receive buffer. Buffers received packets.
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R Virtex-5 FPGA Integrated Endpoint Block Interface Descriptions A pipeline stage can be added in the fabric between the integrated Endpoint and block RAM blocks, if necessary, to meet timing. A pipeline stage can be added for either read or write, or both. It is possible to pipeline address/control or data or both. See “Buffer Latency” in Appendix A for more information.
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R Chapter 2: Integrated Endpoint Block Functionality Ports Table 2-11, Table 2-12, and Table 2-13 define the transmit buffer, receive buffer, and retry buffer ports for the Block RAM interface, respectively.
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R Virtex-5 FPGA Integrated Endpoint Block Interface Descriptions RocketIO transceiver ports in each GTP_DUAL or GTX_DUAL tile. The 0/1 designation is omitted from Table 2-14 for simplicity. For multilane designs, lane 0 should be connected to the RocketIO transceiver channel bonding master. Table 2-14: RocketIO Transceiver Interface Ports Direction Clock Domain PIPERXELECIDLELn Input core_clk Electrical idle detected on receive channel of selected lane.
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R Chapter 2: Integrated Endpoint Block Functionality Table 2-14: RocketIO Transceiver Interface Ports (Continued) Port PIPETXDATAKLn Direction Clock Domain Output core_clk Description Control bits for the transmit data. 0: Data byte 1: Control byte Connect to the TXCHARISK[0] port on the RocketIO transceiver. PIPETXELECIDLELn Output core_clk Electrical idle requested on transmit channel of selected lane. When 1, selects electrical idle on Transmit channel of selected lane.
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R Virtex-5 FPGA Integrated Endpoint Block Interface Descriptions Power Management Interface This interface includes ports related to Power Management. Most ports in this interface are tied off by the CORE Generator wrapper. Table 2-15: Power Management Ports Port L0PWRSTATE0[1:0] Direction Clock Domain Output user_clk Description Indicates the current device power state as follows: 00: D0 01: D1 10: D2 11: D3(1) Can be used to inhibit transfers while the block is in the D1 or D2 state.
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R Chapter 2: Integrated Endpoint Block Functionality Configuration and Status Interface This interface includes control and status, error, backend interface configuration, and interrupt ports. More information on error reporting and user application design considerations can be found in Chapter 4, “Integrated Endpoint Block Operation.” The ports are listed in Table 2-16.
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R Table 2-16: Virtex-5 FPGA Integrated Endpoint Block Interface Descriptions Configuration and Status Ports (Continued) Port L0MACNEGOTIATEDLINKWIDTH[3:0] Direction Clock Domain Output core_clk Description Link width selected after negotiation, as follows: 0001: One lane 0010: Two lanes 0100: Four lanes 1000: Eight lanes L0MACLINKTRAINING Output core_clk Indicates that link training is in progress. Reset to logic 1. Goes Low when the link reaches the L0 state at the end of link training.
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R Chapter 2: Integrated Endpoint Block Functionality Table 2-16: Configuration and Status Ports (Continued) Direction Clock Domain Output core_clk When operating as an Endpoint in a PCIe design, a rising edge on this signal flags the transition from the InitFC1 phase of the initialization procedure to the InitFC2 phase. A falling edge indicates that the link has been broken and is used as a trigger for the link to be reset. There is a bit for each implemented VC. Bits [7:1] are never used.
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R Table 2-16: Virtex-5 FPGA Integrated Endpoint Block Interface Descriptions Configuration and Status Ports (Continued) Direction Clock Domain L0SETCOMPLETERABORTERROR Input user_clk When asserted, causes the relevant Completer Abort status bit(s) to be set to 1. L0SETDETECTEDCORRERROR Input user_clk When asserted, causes the relevant Correctable Error status bit(s) to be set to 1.
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R Chapter 2: Integrated Endpoint Block Functionality Table 2-16: Configuration and Status Ports (Continued) Direction Clock Domain L0SETCOMPLETIONTIMEOUTCORRERROR Input user_clk Asserted to indicate that a requester has not seen a completion and has handled this as a Correctable Error. Causes the relevant “Completion Timeout” status bit(s) to be set to 1.
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R Table 2-16: Virtex-5 FPGA Integrated Endpoint Block Interface Descriptions Configuration and Status Ports (Continued) Direction Clock Domain L0STATSTLPTRANSMITTED Output core_clk L0STATSCFGRECEIVED Output user_clk Port Description Asserted for a single clock cycle when a TLP is transmitted. Asserted for a single cycle of CRMUSERCLK when a configuration packet is received by the configuration block.
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R Chapter 2: Integrated Endpoint Block Functionality Table 2-16: Configuration and Status Ports (Continued) Direction Clock Domain BUSMASTERENABLE Output user_clk Bus Master Enable. When 0, the Endpoint is prevented from issuing any memory or I/O requests. PARITYERRORRESPONSE Output user_clk Parity Error Response. When 1, response to Master Data parity errors has been enabled. SERRENABLE Output user_clk SERR Enable. When 1, reporting of fatal and nonfatal errors has been enabled.
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R Registers Registers The tables in this section describe the registers in the integrated Endpoint block. All registers can be read through the Management interface, and those designated read/write (RW) can also be written. Note that the addresses given in the following tables refer to the Management interface address (MGMTADDR[10:0]). The addresses used when accessing the configuration registers through configuration read and write packets are different, and can be found in the PCI-SIG specifications.
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R Chapter 2: Integrated Endpoint Block Functionality Table 2-17: Legacy Configuration Registers (Continued) Management Address (Hex) MGMTADDR[10:0] Read Only or Read Write Register Name(1) 16 Reserved RO 17 Reserved RO 18 Reserved RO 19 Reserved RO 1A Reserved RO 1B Reserved RO 1C Reserved RO Notes: 1. The register names are listed as they are read on MGMTRDATA[31:0] or written to MGMTWDATA[31:0]. 2.
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R Registers Message Signaled Interrupt (MSI) Capability Structure Table 2-19 summarizes the MSI registers. Table 2-19: MSI Registers Management Address (Hex) MGMTADDR[10:0] Register Name(1) Read Only or Read Write 22 Message Control; Next Pointer; Capability ID RW; RW; RO 23 Message Address RO 24 Message Upper Address RO 25 Reserved (16 bits); Message Data (16 bits) 26 Mask Bits RO 27 Pending Bits RO RO; RO Notes: 1.
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R Chapter 2: Integrated Endpoint Block Functionality Reserved Registers Table 2-21 summarizes the reserved register range. Table 2-21: Reserved Registers Management Address (Hex) MGMTADDR[10:0] Read Only or Read Write Register Name(1) 31 - 45 Address Range is Reserved N/A 49 - 3FF Address Range is Reserved N/A Notes: 1. The register names are listed as they are read on MGMTRDATA[31:0] or written to MGMTWDATA[31:0].
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R Table 2-23: Registers Management Control and Status Registers (Continued) Management Address (Hex) MGMTADDR[10:0] 401 Bit Position Attribute Name Read Only or Read Write 2:0 RETRYRAMWRITELATENCY RW 5:3 RETRYRAMREADLATENCY RW 17:6 RETRYRAMSIZE RW 18 Reserved 19 Reserved 20 Reserved 21 Reserved 24:22 TLRAMWRITELATENCY RW 27:25 TLRAMREADLATENCY RW 0 Reserved 8:1 TXTSNFTSCOMCLK RW 16:9 TXTSNFTS RW 17 Reserved 402 403 20:18 L1EXITLATENCYCOMCLK RW 23:21 L1EXITLATE
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R Chapter 2: Integrated Endpoint Block Functionality Table 2-23: Management Control and Status Registers (Continued) Management Address (Hex) MGMTADDR[10:0] Bit Position 0 405 406 Read Only or Read Write Reserved 3:1 XPMAXPAYLOAD RW 11:4 ACTIVELANESIN RW INFINITECOMPLETIONS RW 12 404 Attribute Name 20:13 Reserved 24:21 XPDEVICEPORTTYPE RW 25 Reserved 26 Reserved 27 Reserved 28 Reserved 29 Reserved 5:0 BAR0MASKWIDTH RW 11:6 BAR1MASKWIDTH RW 17:12 BAR2MASKWIDTH RW
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R Table 2-23: Registers Management Control and Status Registers (Continued) Management Address (Hex) MGMTADDR[10:0] Bit Position Attribute Name Read Only or Read Write 0 BAR0ADDRWIDTH RW 1 BAR1ADDRWIDTH RW 2 BAR2ADDRWIDTH RW 3 BAR3ADDRWIDTH RW 4 BAR4ADDRWIDTH RW 5 Reserved 0 BAR0EXIST RW 1 BAR1EXIST RW 2 BAR2EXIST RW 3 BAR3EXIST RW 4 BAR4EXIST RW 5 BAR5EXIST RW 409 40A 12:0 Reserved 13 Reserved 26:14 Reserved 27 Reserved 12:0 Reserved 13 Reserved 26:1
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R Chapter 2: Integrated Endpoint Block Functionality Table 2-23: Management Control and Status Registers (Continued) Management Address (Hex) MGMTADDR[10:0] Bit Position Attribute Name 12:0 Reserved 13 Reserved 26:14 Reserved 27 Reserved 12:0 Reserved 13 Reserved 26:14 Reserved 27 Reserved 12:0 Reserved 13 Reserved 26:14 Reserved 27 Reserved Read Only or Read Write 410 411 412 12:0 13 VC0RXFIFOLIMITC RW Reserved 413 26:14 27 12:0 13 VC0RXFIFOLIMITNP RW Reserved VC0R
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R Table 2-23: Registers Management Control and Status Registers (Continued) Management Address (Hex) MGMTADDR[10:0] Bit Position 12:0 13 Attribute Name VC0TXFIFOLIMITC Read Only or Read Write RW Reserved 418 26:14 27 12:0 13 VC0TXFIFOLIMITNP RW Reserved VC0TXFIFOLIMITP RW Reserved 419 26:14 27 12:0 13 VC0TXFIFOBASEC RW Reserved VC0TXFIFOBASENP RW Reserved 41A 26:14 41B VC0TXFIFOBASEP RW 27 Reserved 7:0 XPBASEPTR RW 19:8 VCBASEPTR RW 31:20 PMBASEPTR RW 11:0 PBBASEPTR RW
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Chapter 2: Integrated Endpoint Block Functionality 62 www.xilinx.com R Virtex-5 FPGA Integrated Endpoint Block UG197 (v1.
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R Chapter 3 Designing with the Endpoint Block Plus Wrapper Users who are designing with the Virtex-5 FPGA Integrated Endpoint Block for PCI Express designs must use the LogiCORE™ Endpoint Block Plus Wrapper for PCI Express® designs available in the CORE Generator™ tool. This tool provides a wrapper around the integrated Endpoint block and automatically connects the block RAMs, RocketIO transceivers, and reset and clock modules. The wrapper provides an easy-to-use interface that simplifies system design.
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Chapter 3: Designing with the Endpoint Block Plus Wrapper 64 www.xilinx.com R Virtex-5 FPGA Integrated Endpoint Block UG197 (v1.
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R Chapter 4 Integrated Endpoint Block Operation Summary This chapter presents information related to designing with the Virtex-5 FPGA Integrated Endpoint Block. This information assist in understanding the behavior of the block. The Endpoint Block Plus Wrapper uses this information to interface to the Endpoint Block to provide a simple LocalLink interface for user designs.
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R Chapter 4: Integrated Endpoint Block Operation has transmitted. Every time the TL transmits a packet, it increments the count of credits consumed so far. When the transmitted data has exhausted the current credit limit held by the transmitter (the last credit value to be received from the device at the other end of the link), it halts transmission of new data of that type until it receives an UpdateFC packet.
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R Transaction Ordering Transaction Ordering The PCI Express Base Specification has rules about the type of traffic that can overtake other types of traffic to avoid blockages. The PCI Express ordering rules apply at transmission of Transaction Layer packets, and also at reception and transfer through the Transaction Layer interface to the user application. The details are given in “Ordering at Transmission,” page 67 and “Ordering at Reception,” page 67.
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R Chapter 4: Integrated Endpoint Block Operation applied to determine which packet(s) can be legally read in accordance with the PCI strongly ordered model: • A posted packet can be read when LLKRXCHPOSTEDAVAILABLEN is asserted, which allows a posted packet to pass a non-posted or completion packet.
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R Interrupt Handling Disable bit in the PCI Command register is set to 0. This is reflected on the INTERRUPTDISABLE output: • INTERRUPTDISABLE = 0: interrupts enabled • INTERRUPTDISABLE = 1: interrupts disabled (requests are blocked) The MSI Enable bits in the MSI Control register and the Interrupt Disable bit in the PCI Command register are programmed by the Root Complex. The user application has no direct control over these bits.
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R Chapter 4: Integrated Endpoint Block Operation Error Detection The PCI Express Base Specification identifies a number of errors a PCIe port should check for, together with a number of additional optional checks. Most of the required checks (including several of the optional checks) are carried out by the integrated Endpoint block. Some, however, need to be implemented by the user. The integrated Endpoint block performs checks on received TLPs only. The user must perform all checks on transmit TLPs.
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R Table 4-2: Error Detection Error Checking Summary (Continued) PCI Express Check is Where Check is Specification Required Implemented Section or Optional 2.2.7 Optional Endpoint block 7.3.2 Required Endpoint block That Assert_INTx/Deassert_INTx Messages are only issued by upstream Ports. Any Assert_INTx/Deassert_INTx Message that violates this rule is treated as a Malformed TLP. 2.2.8.1 Optional Endpoint block That Assert_INTx/Deassert_INTx Messages use TC0.
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R Chapter 4: Integrated Endpoint Block Operation Table 4-2: Error Checking Summary (Continued) PCI Express Check is Where Check is Specification Required Implemented Section or Optional That Memory Read Request-Locked (MRdLk) requests do not include a payload. Any MRdLk requests with payload must be discarded by the user and a malformed TLP must be signaled. 2.3 Required User That a Completion with Data (CplD) has a 3DW header.
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R Table 4-2: Error Detection Error Checking Summary (Continued) PCI Express Check is Where Check is Specification Required Implemented Section or Optional That the TC associated with each TLP is mapped to an enabled VC at an Ingress Port. Any TLP that violates this rule is treated as a Malformed TLP. 2.5.3 Required Endpoint block That the initial FC value is greater than or equal to the minimum advertisement. Reported as a flow control protocol error.
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R Chapter 4: Integrated Endpoint Block Operation Table 4-2: Error Checking Summary (Continued) PCI Express Check is Where Check is Specification Required Implemented Section or Optional Sequence Number specified by the AckNak_Seq_Num compared with that of unacknowledged TLPs and value in ACKD_SEQ. If no match found: (a) the DLLP is discarded; (b) a DLLP error is reported. 3.5.2.1 Required Endpoint block LCRC field of the received TLP compared with calculated result.
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R Table 4-3: Error Reporting Error Reporting with Integrated Endpoint Block Action Error Detected Action by Integrated Endpoint Block Errors Flagged by Transaction Layer Message generated Flow Control Protocol Error Standard PCIe Error Reporting Legacy Error Reporting ERR_FATAL Action when Receiver Message generated Malformed TLP Standard PCIe Error Reporting Legacy Error Reporting Receiver Overflow Standard PCIe Error Reporting Signaled System Error bit of Status register set (but only if an
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R Chapter 4: Integrated Endpoint Block Operation Table 4-4 summarizes how different types of errors are reported and the actions taken by the user. Table 4-4: Error Reporting with User Action Error Detected Action by User Errors Flagged by Transaction Layer Assert L0SETUSERSIGNALLEDTARGETABORT Action when Transmitter port. (i.e., the Completer) Completer Abort Malformed TLP Action when Receiver (i.e., receiver of the completion) Assert L0SETUSERRECEIVEDTARGETABORT port.
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R Lane Width Lane Width The maximum number of lanes supported by a design using the integrated Endpoint block can be specified through the ACTIVELANESIN and LINKCAPABILITYMAXLINKWIDTH attributes. These attributes should specify the same number of lanes, and a RocketIO transceiver should be connected to the integrated Endpoint block through the Transceiver interface for each lane specified.
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R Chapter 4: Integrated Endpoint Block Operation Known Restrictions This section describes several restrictions and anomalies in the functionality of the integrated Endpoint block for PCI Express® designs. Designers must understand each restriction and the potential impact on their application. This chapter also clearly describes the user action required to work around the restrictions and anomalies. In some cases there are no workarounds available.
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R Known Restrictions 64-Packet Threshold for Completion Streaming on RX Interface The LLKPREFERREDTYPE and LLKRXCH*AVAILABLE signals together allow the user to implement both strict-ordering and relaxed-ordering rules. Relaxed ordering allows completion packets to bypass older posted or non-posted packets available in the receive buffers. For more information on relaxed ordering, refer to Section 2.4 of the PCI Express Base Specification.
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R Chapter 4: Integrated Endpoint Block Operation However, if the posted packets are large and completions are very short, the completion buffer is at risk of overflow when draining the posted packet. The risk is higher if multiple posted or non-posted packets must be drained before switching back to draining completions. Since the risk of completion buffer overflow depends on the traffic pattern, there are three potential workarounds: 1.
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R Known Restrictions Invalid Cycles in LLKRXPREFERREDTYPE Signal Due to the way the integrated Endpoint block updates LLKRXPREFERREDTYPE and the LLKRXCH*AVAILABLE signals, there will be some cycles in which LLKRXPREFERREDTYPE is invalid. Sampling the signal during the invalid cycles can result in incorrect operation.
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R Chapter 4: Integrated Endpoint Block Operation Link Retrain Due to an Absence of UpdateFC DLLPs When the partner device advertises infinite header and data credits for all packet types for a given virtual channel, the integrated Endpoint block might not receive any UpdateFC DLLPs. When the integrated Endpoint block does not receive any UpdateFC DLLPs, it initiates a link retrain because an internal timer used to track the receipt of UpdateFC DLLPs has expired. This behavior is non-compliant.
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R Known Restrictions Workaround To avoid the issues listed, the user needs to prevent non-posted packets and completion packets from being stalled inside the transmit buffer of the integrated Endpoint block. The user needs to monitor the credit status through the management interface and send nonposted and completion packets on the TLI only if sufficient credits are available for transmission.
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R Chapter 4: Integrated Endpoint Block Operation Access to Unimplemented Configuration Space According to PCI Express Specification 1.1, an Endpoint should treat access to an unimplemented configuration space as an unsupported request. The integrated Endpoint block responds with a successful completion that is non-compliant. Workaround There are no workarounds for this issue.
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R Known Restrictions Workaround The user can work around this issue by introducing a delay of 160 ns (equal to 40 CRMCORECLK cycles) in the FPGA logic on the RXELECIDLE 0/1 signals in the interface between the RocketIO transceiver and the integrated Endpoint block. The user can build a single FPGA logic design that turns on the delay whenever L0LTSSMSTATE = Loopback, thus preventing delay during normal operation.
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R Chapter 4: Integrated Endpoint Block Operation Credit Leak When Transmitting Completion TLPs Whenever a minimum size completion TLP (1DW) entering the TX completion buffer causes it to become full and there is a pending configuration completion at the same time, then the configuration completion is incorrectly entered into the TX posted buffer. This results in a reduction of advertised posted credits and no reduction in advertised completion credits, which are both incorrect.
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R Known Restrictions Receipt of Back-to-Back ACK DLLPs Whenever ACKs are received in consecutive cycles for x8 designs, the TX path of the block can lock up. Workaround Users can work around this issue by monitoring the interface between the integrated Endpoint block and the RocketIO transceivers and nullify the second ACK by zeroing out all the bits in the ACK DLLP. This workaound is implemented in LogiCORE Endpoint Block Plus for PCI Express Designs v1.8 or later.
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Chapter 4: Integrated Endpoint Block Operation 88 www.xilinx.com R Virtex-5 FPGA Integrated Endpoint Block UG197 (v1.
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R Chapter 5 Simulating with the Integrated Endpoint Block For simulation information, refer to UG343, LogiCORE IP Endpoint Block Plus for PCI Express Getting Started Guide. The Getting Started Guide discusses how to set up and simulate the Endpoint Block Plus Wrapper using the integrated Endpoint block for PCI Express designs. Virtex-5 FPGA Integrated Endpoint Block UG197 (v1.5) July 22, 2009 www.xilinx.
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Chapter 5: Simulating with the Integrated Endpoint Block 90 www.xilinx.com R Virtex-5 FPGA Integrated Endpoint Block UG197 (v1.
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R Appendix A Integrated Endpoint Block Attributes Summary This appendix lists the attributes that must be set for the Virtex-5 FPGA Integrated Endpoint block. All attributes are set in the Endpoint Block Plus wrapper, based on choices made in the CORE Generator GUI, and are documented here for reference.
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R Appendix A: Integrated Endpoint Block Attributes interspersed with smaller packets. Care should be taken in opting to specify a larger number of packets than the FIFO technically has room for, to ensure that allowance has been made for effects that ordering rules can have on the packets needing to be handled. The other factor that needs to be considered is the absolute limit of eight packets that can be handled by any FIFO.
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R Table A-2: Initial Flow Control Credits Memory Interface Read Latency Settings Block RAM Number of Number of Fabric TLRAMREADLATENCY or Output Fabric Pipeline Pipeline Stages RETRYRAMREADLATENCY Setting Registers Used Stages (Data) (Address/Control) Notes 1 0 0 011b Typical setting 1 1 1 101b For very large buffer sizes implemented in slow speed grade parts The write latency attribute settings are calculated as: # of fabric write pipeline stages (address and data) +1 Write Latency Setting
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R Appendix A: Integrated Endpoint Block Attributes • Infinite Completions are indicated by setting the flow control credit attribute to 0, and setting the INFINITECOMPLETIONS attribute to TRUE. • Each posted data credit is 16 bytes. • The maximum number of packets that can be buffered by each FIFO is eight. Thus, the maximum number of posted data or completion data credits that should be advertised is 8 × XPMAXPAYLOAD/16.
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R Extended Capabilities Table A-5: Default Pointer Attribute Settings (Continued) Attribute Value Notes PMCAPABILITYNEXTPTR MSIBASEPTR MSICAPABILITYNEXTPTR XPBASEPTR PCIECAPABILITYNEXTPTR 0 Cannot be changed. AERCAPABILITYNEXTPTR PBBASEPTR Cannot be changed. DSNBASEPTR Cannot be changed. PBCAPABILITYNEXTPTR DSNCAPABILITYNEXTPTR Should not be changed for PCIe compliant systems. VCBASEPTR VCCAPABILITYNEXTPTR 0 Cannot be changed. Two linked lists are defined.
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R Appendix A: Integrated Endpoint Block Attributes Integrated Endpoint Block Attributes Table A-7 summarizes the integrated Endpoint block attributes. Table A-7: Integrated Endpoint Block Attributes Attribute Name Type Description VC0TXFIFOBASEP 13-bit Hex Base of address area used for header and data of transmitted posted packets associated with VC0. Must be set to 0. VC0TXFIFOBASENP 13-bit Hex Base of address area used for header and data of transmitted non-posted packets associated with VC0.
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R Table A-7: Integrated Endpoint Block Attributes Integrated Endpoint Block Attributes (Continued) Attribute Name Type Description VC0RXFIFOBASEP 13-bit Hex Base of address area used for header and data of received posted packets associated with VC0. Must be set to 0. VC0RXFIFOBASENP 13-bit Hex Base of address area used for header and data of received non-posted packets associated with VC0.
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R Appendix A: Integrated Endpoint Block Attributes Table A-7: Integrated Endpoint Block Attributes (Continued) Attribute Name ACTIVELANESIN Type 8-bit Hex Description Bit mask of available active lanes. Valid settings are: 01h: x1 03h: x2 0Fh: x4 FFh: x8 TXTSNFTS Integer Sets the number of FTS sequences generally advertised in the TS1 Ordered Sets (used for all lanes).
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R Table A-7: Integrated Endpoint Block Attributes Integrated Endpoint Block Attributes (Continued) Attribute Name L0SEXITLATENCYCOMCLK Type Integer Description Sets the exit latency from the L0s state to be applied where a common clock is used. Transferred to the Link Capabilities register.
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R Appendix A: Integrated Endpoint Block Attributes Table A-7: Integrated Endpoint Block Attributes (Continued) Attribute Name BAR1ADDRWIDTH Type Integer Description Specifies BAR 1 address width. Valid settings are: 0: 32 bits wide 1: 64 bits wide When 64-bit addressing is selected, the BAR occupies both the BAR1 and BAR2 registers. BAR2ADDRWIDTH Integer Specifies BAR 2 address width.
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R Table A-7: Integrated Endpoint Block Attributes Integrated Endpoint Block Attributes (Continued) Attribute Name BAR5PREFETCHABLE Type Boolean Description Specifies BAR 5 memory region is prefetchable. Valid settings are: TRUE: prefetchable FALSE: not prefetchable BAR0IOMEMN Integer Selects Memory or I/O Space for BAR 0. Valid settings are: 0: Memory Space 1: I/O Space BAR1IOMEMN Integer Selects Memory or I/O Space for BAR 1.
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R Appendix A: Integrated Endpoint Block Attributes Table A-7: Integrated Endpoint Block Attributes (Continued) Attribute Name XPDEVICEPORTTYPE Type 4-bit Hex Description Identifies the type of device/port as follows: 0h: Endpoint device for PCI Express designs 1h: Legacy Endpoint device for PCI Express designs Transferred to PCI Express Capabilities register (see Table 2-20, page 55). XPMAXPAYLOAD Integer Specifies maximum payload supported.
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R Table A-7: Integrated Endpoint Block Attributes Integrated Endpoint Block Attributes (Continued) Attribute Name PMCAPABILITYDSI Type Boolean Description Device Specific Initialization (DSI). TRUE: 1 FALSE: 0 Transferred to the PM Capabilities register. PMCAPABILITYAUXCURRENT 3-bit Hex Reserved. Must be set to 0h. PMCAPABILITYD1SUPPORT Boolean D1 Support. Transferred to the PM Capabilities register. Must be set to FALSE. PMCAPABILITYD2SUPPORT Boolean D2 Support.
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R Appendix A: Integrated Endpoint Block Attributes Table A-7: Integrated Endpoint Block Attributes (Continued) Attribute Name MSICAPABILITYMULTIMSGCAP Type 3-bit Hex Description Multiple Message Capable. Each MSI function can request up to four unique messages. System software can read this field to determine the number of messages requested.
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R Table A-7: Integrated Endpoint Block Attributes Integrated Endpoint Block Attributes (Continued) Attribute Name Type LINKSTATUSSLOTCLOCKCONFIG Boolean Description Slot Clock Configuration. Indicates where the component uses the same physical reference clock that the platform provides on the connector. For a port that connects to the slot, indicates that it uses a clock with a common source to that used by the slot.
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R Appendix A: Integrated Endpoint Block Attributes Table A-7: Integrated Endpoint Block Attributes (Continued) Attribute Name Type Description PBCAPABILITYDW0DATASCALE 2-bit Hex Reserved. Must be set to 0h. PBCAPABILITYDW0PMSUBSTATE 3-bit Hex Reserved. Must be set to 0h. PBCAPABILITYDW0PMSTATE 2-bit Hex Reserved. Must be set to 0h. PBCAPABILITYDW0TYPE 3-bit Hex Reserved. Must be set to 0h. PBCAPABILITYDW0POWERRAIL 3-bit Hex Reserved. Must be set to 0h.
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R Table A-7: Integrated Endpoint Block Attributes Integrated Endpoint Block Attributes (Continued) Attribute Name AERBASEPTR Type 12-bit Hex Description Location of the base of the Advanced Error Reporting Capability Structure. See Table A-6, page 95 for more information. Not supported. DSNBASEPTR 12-bit Hex Location of the base of the Device Serial Number Capability Structure (Table 2-22, page 56). See Table A-6, page 95 for more information.
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Appendix A: Integrated Endpoint Block Attributes 108 www.xilinx.com R Virtex-5 FPGA Integrated Endpoint Block UG197 (v1.
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R Glossary Click on a letter, or scroll down to view the entire glossary. The PCI Express Base 1.1 Specification also includes a Terms and Acronyms section. 8ABCDEFGHIJKLMNOPQRSTUVWXYZ 8 8B/10B Encoding An encoding method used for encoding 8-bit data bytes as 10-bit Transmission Characters to acheive the following: bit synchronization, DC balance, a simplified design for receivers and transmitters, improved error detection, and easy identification of control characters. An example is shown below.
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R B BAR Base Address Register. Beat A clock cycle where both the source and destination are ready. C Completer The device addressed by a request. It executes the completer transaction. Completion A Packet used to terminate or partially terminate a transaction sequence. Configuration Space One of the four address spaces within the PCI Express architecture (the others are I/O, memory and message). Packets with a Configuration Space address are used to configure a device. CplD Completion with Data.
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R D Data Link Layer The middle layer of the PCI Express architecture, that is between the Transaction Layer and the Physical Layer. See “Data Link Layer” on page 19. Digest A single 32-bit DW at the end of a TLP, containing an ECRC value. DL_Down DL_Down status indicates that there is no connection with another component on the Link, or that the connection with the other component has been lost and is not recoverable by the Physical or Data Link Layer. DLLP Data Link Layer Packet.
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R Function A logical function corresponding to a PCI function configuration space. Can be used to refer to one function of a multi-function device, or to the only function in a single-function device. G H Hot plug The ability to swap cards in a powered up system using software control. Hot swap The ability to swap cards in a powered up system without software control. I In-band Communications that use the differential wire pairs of the PCI Express lanes for signaling.
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R L Lane A set of differentially driven signal lines, one for each direction of data flow. A 1-lane PCI Express implementation is sometimes referred to as “x1” (by-1), a 4-lane implementation “x4” (by-4), and so on. LCRC Link CRC. A CRC added by the Data Link Layer, that covers the entire TLP and the sequence number. It is checked by the neighboring receiver device. Legacy Interrupt PCI interrupt delivery using active Low INTA signal. Link A communication path between two PCI Express components.
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R O Ordered set The sequences of multiples of four characters starting with a comma (COM) character. These special sequences of characters are used during link training, clock compensation, electrical idle, and L0s exit. P Packet A unit of data transferred across a PCI Express Link. The three types of packets are TLPs, DLLPs, and PLPs. PB Power Budgeting. Physical Layer The lowest of the three layers in the PCI Express architecture. See “Physical Layer” on page 19. PM Power Management.
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R S Sideband A signal that is implemented with its own wire. Communication using a sideband signal is not “in-band”. Required by certain PCI Express form factors. Sticky register A register that retains its state through a hot reset. Switching fabric The combination of hardware and software that moves data coming in to a network node out the correct port to the next node in the network.
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R multiple virtual channels. There is no correspondence between the number of virtual channels and the number of Lanes. W X x1, x2, x4, x8, etc. A notation for designating how many lanes are included in the PCI Express link (1, 2, 4, 8 in this example). Pronounced by 1, by 2, by 4, by 8, etc. Y Z 116 www.xilinx.com Virtex-5 FPGA Integrated Endpoint Block UG197 (v1.
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Index A base_addr3_mask register 53 DLLTXPMDLLPOUTSTANDING port 52 base_addr4_mask register 53 DSNBASEPTR attribute 94, 95, 107 ACTIVELANESIN attribute 24, 58, 77, 98 base_addr5_mask register 53 DSNCAPABILITYNEXTPTR attribute 95, AERBASEPTR attribute 94, 95 buffer capacity 41 buffer latency 92 buffer layout 91 AERCAPABILITYNEXTPTR attribute 95, 105 AUXPOWER port 52 BUSMASTERENABLE port 52 105 E Endpoint Cap ID register 55 B BAR0 register 53 BAR0ADDRWIDTH attribute 59, 99 BAR0EXIST attribute 5
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R L0MACRXL0SSTATE port 45 L0STATSDLLPTRANSMITTED port 50 LLKTXSOFN port 29, 35 L0MSIENABLE0 port 50 L0STATSOSRECEIVED port 50 LLKTXSRCDSCN port 34 L0MSIREQUEST0 bus 50 L0STATSOSTRANSMITTED port 50 LOWPRIORITYVCCOUNT attribute 57, L0MULTIMSGEN0 bus 50 L0STATSTLPRECEIVED port 50 L0PACKETHEADERFROMUSER bus 52 L0STATSTLPTRANSMITTED port 51 L0PMEACK port 45 L0TRANSACTIONSPENDING port 48 L0PMEEN port 45 L0UNLOCKRECEIVED port 52 L0PMEREQIN port 45 L1EXITLATENCY attribute 57, 99 Mask Bits regist
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R Next Pointer register 55 PCIECAPABILITYNEXTPTR attribute 95, 104 P PARITYERRORRESPONSE port 52 PBBASEPTR attribute 94, 95, 105 PBCAPABILITYDW0BASEPOWER at- tribute 105 PBCAPABILITYDW0DATASCALE at- tribute 106 PBCAPABILITYDW0PMSTATE attribute 106 PBCAPABILITYDW0PMSUBSTATE at- tribute 106 Pending Bits register 55 PIPEDESKEWLANESLN port 44 PIPEPHYSTATUSLN port 43 PIPEPOWERDOWNLN bus 44 PORTVCCAPABILITYVCARBTABLEOFFSET attribute 105 Power Management Capabilities register 54 Power Management Control
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R T TLRAMREADLATENCY attribute 57, 98 TLRAMREADLATENCY port 32 TLRAMWRITELATENCY attribute 57, 98 TX buffer 15, 21, 25, 29, 35, 40, 41, 42, 91, 92, 98 TX Link 45 TXTSNFTS attribute 57, 98 TXTSNFTSCOMCLK attribute 57, 98 U URREPORTINGENABLE port 52 V VC0RXFIFOBASEC attribute 60, 91, 97 VC0RXFIFOBASENP attribute 60, 91, 97 VC0RXFIFOBASEP attribute 60, 91, 93, 97 VC0RXFIFOLIMITC attribute 60, 91, 93, 97 VC0RXFIFOLIMITNP attribute 60, 91, 97 VC0RXFIFOLIMITP attribute 60, 91, 93 VC0TOTALCREDITSCD attribut