Specifications

SLAA154

Interfacing the TLV320AIC12/13/14/15 Codec to the TMS320C5402™ DSP 7

The following equations determine the respective frequencies:

• FS (frame synchronization frequency) = MCLK / (16 * M * N * P). Reference [1] provides a

complete description of the programmable M, N, and P parameters. These parameters are

programmed through control register four (CR4). To specify the value for M, bit D7 of CR4

must be set, and the value specified in bit locations D0 through D6 are assigned to it. To

specify the parameters N and P, bit D7 of CR4 must be cleared, and the values specified in

bit locations D3 through D6; and D0 through D2 respectively are assigned to parameters N

and P.

• SCLK (serial shift clock) = FS * MD * PM. Where MD is number of devices in cascade, and

PM is the data transfer mode. The data transfer mode is selected by setting or clearing the

bit location D6 of CR1. Clearing this bit selects the programming mode, while setting this bit

selects the continuous mode. The value of PM is 2 for the program mode, and 1 for the

continuous mode.

3.4 Interface Data Format

Upon reset, the DAC input data length option of 15 bit + one LSB bit option is selected.

Numerical information is communicated to the codec through the DIN terminal of the codec and

the DX terminal of the DSP. Through this channel, both the codec’s control registers and DAC

input registers are programmed. Data communication between the ADC of the codec and the

DSP is conducted through the DOUT terminal of the codec and the DR terminal of the DSP.

In the programming mode, (D6 of CR1 cleared), each data frame contains two 16 bit blocks of

data information for each device in cascade. See the illustration below. In this mode, the data

frame of the DIN terminal carries 16-bit data from the DSP to the codec’s DAC data register, and

the control frame of the DIN terminal carries the configuration instructions from the DSP to the

codec. The format for this configuration instruction is discussed later. The data frame of the

DOUT terminal carries the numerical results of the codec’s ADC to the DSP, while the control

frame carries the data content of the register being read, back to the DSP.

DIN / DOUT

Master Data

Slave Data

Master Control

Slave Control

Master Data (next frame)

Slave Data (next frame)

Master Control (next frame)

Slave Control (next frame)

Figure 3. Master / Slave Communication in Programming Mode