Specifications

SLAA154
6 Interfacing the TLV320AIC12/13/14/15 Codec to the TMS320C5402™ DSP
3.2 Analog Interface
The AIC12 device has a full complement of analog input and output terminals that facilitate
modern digital telephony and voice communication. The AIC12 codec has three software
selectable analog inputs and three programmable outputs. The selection of these analog inputs
and outputs is determined by the programmed statuses of the D1 and D2 bits, and the D7, D3,
and D4 bits of the configuration register CR6 respectively.
3.2.1 Analog Inputs
The analog input sources are:
• The MICIN accommodates a single-ended microphone interface, and a higher quality
pseudo differential microphone interface. In the case of the pseudo differential
configuration, a single-ended input signal is internally converted to a differential signal
before being digitally processed. An on-chip front-end programmable pre-amplification
circuit is provided to allow the use of a wide range of microphones. Amplification selection
of 0, 6, 12, and 24 dB can be made by properly programming the bits D0 and D1 of
configuration register 5C.
• There are also two pairs of differential analog inputs, INP1/INM1 and INP2/INM2. This
differential configuration provides good common-mode rejection of undesirable analog
signals. These inputs could also be configured for single-ended operation.
Note that all the analog inputs are self-biased at 1.35 volts.
3.2.2 Analog Outputs
The analog outputs of this codec are the differential outputs of the DAC channel. They have
different drive specifications.
• TheOUTP1/OUTM1candirectlydrivealoadof600Ω in either a single-ended mode or a
differential mode.
• The OUTP2 and OUTP3 are outputs from two programmable gain amplifiers. They can
drive output loads of 16 Ω directly, and are configurable for either single-ended or
differential operation mode.
3.3 Digital Interface
The interaction between the DSP system is conducted through the smart time division
multiplexed (SMARTDM) serial port. The McBSP1 port of the C5402™ DSP provides this
interface. In master mode, the codec generates the serial clock (SCLK) from the system
supplied master clock (MCLK). Its frequency depends on the following parameters and settings:
• MCLK frequency
• The number of codecs cascaded—two in this case (master and one slave)
• The data transfer mode selected—programming mode or continuous mode, and
• The programmed selection of the M, N, and P timing parameters