Specifications

SLAA154
4 Interfacing the TLV320AIC12/13/14/15 Codec to the TMS320C5402™ DSP
In the Figure 1, note that the reset and power-down signals must be synchronized to the main
clock (MCLK) of the codec. For more information see reference [5]. Also note that the maximum
frequency of MCLK is 100MHz
2.2 Basic Two-AIC12 Cascade Codec/DSP Interface
The typical circuit for the two AIC12 devices in cascade operation mode is given in Figure 2. As
in the case of the stand-alone operation, the reset and power-down signals must be
synchronized to the main clock (MCLK). Also, the signal edge time difference from one codec to
another should be within 2ns.
2.3 Codec/C5402™ DSP Starter Kit System
To develop this application report, a codec/DSP system was built using a TMSC5402™ DSP
starter kit board, a TLV320AIC development platform board, and an AIC12 EVM board. The AIC
development platform is the bridge between the AIC12 EVM board and the C5402™ DSP starter
kit. Refer to Figure 3 in reference [5] for the system layers and board-to-board connections. The
system connections are based on the interface concept illustrated in Figure 1 or Figure 2.
More information is available for the C5402™ DSP EVM board at TI’s website:
http://focus.ti.com/docs/tool/toolfolder.jhtml?PartNumber=TMDS320005402
.
Also refer to [6] for additional information on the codec development and AIC12 EVM boards.
Before powering up the system, board jumpers and switches need to be properly set up. This
process is called the hardware configuration. The C5402™ DSP starter kit board is configured
according to Tables 3 and 4 in reference [5]. Also, see the Test Procedures for AIC12 section in
this report. The codec’s hardware configuration consists primarily in setting the logic state of
pins M/S and FSD. Under the stand-alone master mode, the M/S should be logic high and the
FSD should be pulled high—see Figure 1. When using the two-AIC12 cascade mode, the first
AIC12 (whose FS is connected to the DSP), is always the master. The second AIC12, and the
DSP are slaves. The hardware configuration under the cascade mode is shown in Figure 2.
3 Software Interface
The AIC12/C54x™ DSP is configured for a master and one slave cascade setup, in which the
codec provides all serial shift clock and frame synchronization. The complete software code
required for configuring the DSP for this mode of operation can be downloaded from the product
folder at TI’s website (www.ti.com). More detailed information on the AIC12 codec can be
obtained in reference [1]. Detailed explanations of the software programs can be found in
reference [5]. This includes the DSP memory map register (MMR) configuration, the DSP
system clock control setup, the McBSP initialization routine, and the control loop timing routine.
3.1 Codec Control Register Initialization
There are six control registers (CR) in an AIC12 device. These give users the option to select
and control the codec’s functions. For definitions of these registers, refer to the data manual [1].
The following sections address the basic AIC12 initialization guideline, issues, and other
important points.