Specifications

SLAA154
12 Interfacing the TLV320AIC12/13/14/15 Codec to the TMS320C5402™ DSP
With the scope in the single trigger mode, and set the scope sync to trigger on the rising edge of
the TP12 signal, press the reset push button on the development platform. Confirm that the
rising edge of SYNC RESET occurs on the rising edge of MCLK. Then set the scope sync to
trigger on the falling edge of the TP12 signal; again press the reset push button on the
development platform. Confirm that the falling edge of SYNC RESET also occurs on the rising
edge of MCLK.
5.3 AIC12 EVM Board
Set the jumpers on the EVM board as follows:
Table 4. AIC12 EVM Board Jumpers
Jumper Setting Condition
W1 1–2 U2ismaster
W2 1 – 2 Make the selection options for FSD_1 a logic 1 or FS_2
W3 2–3 PassFSD_1throughtoFS_2
W4 2 – 3 Select J3 pin #1 as signal source for INM1_b (negative input)
W5 2 – 3 Select J5 pin #2 as signal source for INM1_a (negative input)
W6 1 – 2 OUTP1_b is routed directly to J6 Pin #2
W7 1 – 2 OUTP1_a is routed directly to J7 Pin #2
W8 Closed Connect AGND to DGND
W9 Closed Connect AGND to DRV_AGND
W10 Closed Do not isolate the secondary AIC unit from the primary AIC unit
P1 9 – 10 Top EVM Card: FSD_x (Last) is pulled High
P1 11 – 12 Top EVM Card: GBL_SCL is pulled high (I
2
C communication)
P1 13 – 14 Top EVM Card: GBL_SDA is pulled high (I
2
C communication)
With the above settings, if the C5402™ DSP development platform (DSK) and the EVM board
are properly connected—applying power to the system and pressing the RESET push button
produces the EVM test point signals listed in the following table:
Table 5. EVM Test Point Signals
Test Point Signal Default Frequency (Two AIC12 Devices)
TP8 SCLK 260.416 kHz
TP9 FS_1 4.069 kHz
TP10 DXa / DIN N / A
TP11 DRA/DOUT N/A
TP12
SYNC RESET
Logic 1
TP13
SYNC PWDN
Logic 1
Default settings:
M=16
N=6
P=8
FS=MCLK/(16*M*N*P)=4.069kHz.
SCLK = FS * 4 * 16 = 260.416 kHz. (Program Mode)