Specifications

SLAA154
Interfacing the TLV320AIC12/13/14/15 Codec to the TMS320C5402™ DSP 11
5 Test Procedure for AIC12.
5.1 TLV320AIC Development Platform Board Setup
1. Select the 3.3 V source from the DSP (DSP_3.3VDC), by setting the jumper W1 for 1-2.
2. Plugging the TLV320AIC development platform to the DSP DSK through the common
connector turns on the two yellow LEDs, D1 and D2.
3. Confirm that the digital and analog power sources, and grounds are properly isolated.
4. Confirm the following voltage levels on the listed test points, and J3 pins.
Table 2. Test Point Voltage Levels
Voltage Level Test Points Reference Point J3 Pin Number
3.3 VDC (Digital) TP2 TP3 25 & 27
3.3 VDC (Analog) TP5 TP4 37 &39
3.3 VDC (A/Drive) TP6 TP4 33 & 35
1.8 VDC TP1 TP3 29 & 31
Ground (Digital) TP3 TP3 2, 4, 6, 28, 30 & 32
Ground (Analog) TP4 TP4 34, 36, 38 & 40
5. Set the development platform such that the system clock is derived from the DSP DSK,
50 MHz, by selecting the 1-2 setting on jumper W2. Confirm that the clock frequency is
actually 50 MHz. Note that there is a 100 MHz clock option onboard the development
platform. However, for the particular selection for M, N, and P in the associated test
software, this option should not be selected.
Table 3. Development Platform Jumpers
Jumper Setting Condition
W1 1 – 2 Analog 3.3 V is driven from the DSP DSK.
W2 1 – 2 Select 50 MHz clock source for driving MCLK
W3 Open
CNTLa does not drive the power-down (SYNC PWDN) circuit.
5.2 SYNC RESET Synchronization Test
Test and make sure that the rising edge of the SYNC RESET signal is properly synchronized to
the MCLK.
Place the scope probes on the following test points:
1. TP12 (SYNC RESET)
2. TP7 (Reset Switch & DSP Reset Signal)
3. J3 Pin 1 (MCLK)