Specifications

SLAA154
10 Interfacing the TLV320AIC12/13/14/15 Codec to the TMS320C5402™ DSP
Table 1. Control Register Address Chart
Register Address D15 D14 D13 Register Name
0 0 0 0 No Operation
1 0 0 1 Control Register 1 (CR1)
2 0 1 0 Control Register 2 (CR2)
3 0 1 1 Control Register 3 (CR3)
4 1 0 0 Control Register 4 (CR4)
5 1 0 1 Control Register 5 (CR5)
6 1 1 0 Control Register 6 (CR6)
2. In the read mode, bit D12 of the DIN control data stream is set, while in the write mode,
the D12 bit is cleared.
3. In the write mode, if the user wishes to program a particular register with a common value
for all the codecs within the cascade, set the broadcast bit, D11. This forces the contents
of the lower 8-bits of the DIN bit stream to be programmed into that specified control
register for all the codec devices in the cascade. If D11 is cleared, then only the
corresponding AIC device is programmed. This bit must be set to 0 in the read mode.
4. Bits D8 through D10 must always be set in the read or write mode.
5. The data to be written to the codec should be programmed in the lower 8-bits of the DIN
data stream. For a read instruction, this lower byte is don’t care.
If a read instruction was issued, i.e. bit D12 of DIN bit stream is set in the same cycle, and within
the same device slot, the content of the register of the corresponding codec device is pumped
out of the DOUT terminal of the codec. The first 4 bits of the stream indicate the SMARTDM
device address of the respective codec, the next three bits carry the register address for the
register being read. Bit 8 is reserved and always 0. The lower 8-bits of the output data stream,
DOUT (read), contain the content of the codec’s register.
4 Design Issues
The jumper settings for the AIC12 EVM board used for this application note are provided in the
section on test procedures for the AIC12.
The first task to be performed during the AIC12 initialization is to read the CR1 of all codecs in
the cascade at least once. This is necessary in order to clear the overflow flags of any of the
codec’s ADC and DAC, ADOVF (D7) and DAOVF (D4) in CR1 that might have been set as a
result of any previous conversions. This is because once either of these flags has been set in
any of the codecs; the flag remains set until the user reads the CR1. Reading this control
register automatically resets the overflow flags.
It is most important to remember that there can only be one master in the cascaded system.
The reset and power-down signals must be synchronized to the main clock (MCLK), and the
signal edge timing difference from one codec to another should be within 2ns. And most
importantly, MCLK must not exceed 100 MHz.