Unit installation

MAX+PLUS II Getting Started
338 Altera Corporation
timing analysis displayed in the
MAX+PLUS II Timing Analyzer.
timing assignment An assignment that
specifies desired speed performance on
one or more logic functions.
The t
PD
, t
SU
, t
CO
, and f
MAX
timing
assignments, as well as Òtiming cuts,Ó are
available. You can assign timing to
individual logic functions and specify
default timing for the project as a whole.
Timing assignments influence project
compilation only for the FLEX 6000,
FLEX 8000, and FLEX 10K device families.
timing cut A type of timing assignment
that cuts the connections between the
timing path for an individual node and
other nodes in the project, to indicate that
the Compiler should not consider the delay
along this path when it attempts to meet
the userÕs desired speed performance
while processing the project.
t
PD
(input to non-registered output delay)
The time required for a signal from an
input pin to propagate through
combinatorial logic and appear at an
external output pin.
t
PD
is also a timing assignment that
specifies the maximum acceptable input to
non-registered output delay. In
MAX+PLUS II, you can specify a required
t
PD
for an entire project and/or for any
input pin (INPUT or INPUTC), output pin
(OUTPUT or OUTPUTC), or TRI buffer (i.e.,
BIDIR or BIDIRC pin output function)
pin.
tri-state buffer A buffer with an input,
output, and controlling Output Enable
signal. If the Output Enable input is high,
the output signal equals the input. If the
Output Enable input is low, the output
signal is in a state of high impedance. The
tri-state buffer is implemented with the
TRI primitive.
Tri-state buses can be implemented by
tying multiple nodes together in a Graphic
Editor file and with the TRI_STATE_NODE
variable in an AHDL file.
t
SU
(Clock setup time) The length of time
for which data that feeds a register via its
data or Enable input(s) must be present at
an input pin before the Clock signal that
clocks the register is asserted at the Clock
pin.
t
SU
is also a timing assignment that
specifies the maximum acceptable Clock
setup time. In MAX+PLUS II, you can
specify a required t
SU
for an entire project
and/or for any input pin (INPUT or
INPUTC) or bidirectional pin (BIDIR or
BIDIRC input function).
TTF see Tabular Text File.
Turbo Bit and logic cell Turbo Bit A control
bit for choosing speed and power
characteristics of an Altera device. The
Turbo Bit logic option is most effective
when applied to megafunctions,
macrofunctions, and pins. If the Turbo Bit
is on, the speed increases; if it is off, the
power consumption decreases. The Turbo
Bit can be turned on or off in a design file or
the Compiler.
Turbo Bit availability differs for each
device family
81_GSBOOK.fm5 Page 338 Tuesday, October 14, 1997 4:04 PM