Unit installation

MAX+PLUS II Getting Started
334 Altera Corporation
separated by two periods. Each number in
the sequence represents an individual node
(or Òbus bitÓ). The identifier cannot end
with a digit.
Example: group a[4..1] consists of the
nodes a4, a3, a2, and a1.
In a Graphic Editor files, a sequential bus
name can also include one or more single-
range bus names in a series. The first node
of the series or the first node in the first
range is the most significant bit of the bus;
the last node of the series or the last node in
the last range is the least significant bit.
Example: a[8..0], b1, dout[6..4]
SNF see Simulator Netlist File.
SOF see SRAM Object File.
source node A node that is tagged
(designated) as the source of a signal for
the purpose of timing analysis. A source
node is tagged with the Timing Analysis
Source command (Utilities menu), and can
be any node that is the output of a
primitive, megafunction, macrofunction,
or I/O pin.
spike see glitch.
SRAM Object File (.sof) A binary file (with
the extension .sof), generated by the
CompilerÕs Assembler module, that
contains the data for configuring an Altera
FLEX 6000, FLEX 8000, or FLEX 10K
device.
Standard Delay Format Output File (.sdo)
An optional output file (with the extension
.sdo) containing timing delay information
that allows you to perform back-
annotation for simulation with VHDL
simulators that use simulation libraries
that are compliant with VITAL version 2.2b
and version 3.0 (VITAL 95); back-
annotation for simulation in Verilog HDL
simulators; and timing analysis and
resynthesis with EDIF simulation and
synthesis tools.The Standard Delay Format
(SDF) is an industry-standard format.
The MAX+PLUS II CompilerÕs EDIF,
VHDL, and Verilog Netlist Writer modules
of the MAX+PLUS II Compiler can
generate SDF Output Files in SDF version
2.1 or 1.0 format.
standard synthesis Logic synthesis that
includes the following logic options:
■ Fast I/O
■ Global Signal
■ Hierarchical Synthesis
■ Insert Additional Logic Cell
■ Minimization (Full and Partial)
■ NOT Gate Push-Back
■ Parallel Expanders
■ Slow Slew Rate
■ SOFT Buffer Insertion
■ Turbo Bit (including logic cell Turbo
Bit)
■ Use LPM for AHDL Operators
■ XOR Synthesis
Standard synthesis includes only these
logic options; other options listed in the
Define Synthesis Style and Advanced
Options dialog boxes (Assign menu) are
available only in multi-level synthesis. This
type of logic synthesis is available only for
the Classic, MAX 5000, MAX 7000, and
MAX 9000 device families.
state bit An output of a flipflop used by a
state machine to store one bit of the value of
the state machine.
81_GSBOOK.fm5 Page 334 Tuesday, October 14, 1997 4:04 PM