Unit installation

Glossary
Altera Corporation 325
Glossary
Glossary
Normal logic synthesis style The Altera-
provided style that directs the Logic
Synthesizer to optimize your project for
minimum silicon resource usage.
The Normal style attempts to use device
resources as efficiently as possible, without
adding excessive timing delays.
To display the settings for this style, select
the style in the Define Synthesis Style
dialog box, which is available through the
Logic Options or Global Project Logic
Synthesis dialog boxes (Assign menu).
1 If the global project logic synthesis
style for your project is not fully
defined, i.e., if the style specified
with the Global Project Logic
Synthesis command (Assign menu)
uses a ÒdefaultÓ setting for any logic
option, the MAX+PLUS II Compiler
will use the non-ÓdefaultÓ setting for
that logic option from the
predefined, Altera-provided settings
for the Normal style. To view the
settings for a predefined style, open
the Define Synthesis Style dialog
box, select the style in the Style box,
and choose the Use Default button.
O
object-by-object selection The process of
selecting multiple non-contiguous objects.
The first object is selected by clicking
Button 1 on it. You can add or remove
objects to the selection by pressing Shift
while clicking on them with Button 1.
In the Graphic Editor, object-by-object
selection can be used to select graphics
and/or text blocks; in the Waveform
Editor, to select nodes and groups; in the
Floorplan Editor, to select pins, nodes,
logic cells, or assignment bins; and in the
Hierarchy Display, to select file icons.
In the Graphic Editor, multiple objects in a
rectangular area can be selected and added
to an existing selection by pressing Shift
while dragging Button 1.
octal The base 8 number system (radix).
Octal digits are 0 though 7.
Octal numbers are indicated with the
following notation:
Examples:
Q"4671223" (AHDL)
8#4671223# (VHDL)
'o4671223 (Verilog HDL)
one-hot encoding A type of binary coding
in which one and only one bit of a value is
set to 1. For example, the four legal values
0001, 0010, 0100, and 1000 together
COMB Node or group is fed by
combinatorial logic, e.g., an
AND gate.
REG Node or group is fed by a
register (implemented with a
logic cell on the device).
MACH Node is fed by a state machine.
Type: Meaning:
Language Notation
AHDL O"<series of digits 0 to 7 >"
or
Q"<series of digits 0 to 7 >"
VHDL 8#<series of digits 0 to 7 >#
Verilog HDL 'o<series of digits 0 to 7 >
81_GSBOOK.fm5 Page 325 Tuesday, October 14, 1997 4:04 PM