Unit installation

MAX+PLUS II Getting Started
302 Altera Corporation
C
chip A group of logic functions defined as
a single, named unit. A chip is assigned to
an actual device by either the user or the
Compiler.
You can make chip assignments on logic
functions in design files. Items that are
assigned to the same chip are placed in the
same device during compilation. The term
device always refers to an actual
programmable logic device, whereas the
term chip always refers to a group of logic
functions.
When the Compiler processes a project,
each chip name is assigned to a
corresponding programming file for a
particular device.
Classic An Altera device family based on
AlteraÕs original EPROM-based EPLD
architecture. MAX+PLUS II provides
support for the following Classic devices:
EP600I, EP610, EP610I, EP900I, EP910,
EP910I, EP1800I, and EP1810 devices.
Clear An input signal that resets a
register. A synchronous Clear signal resets
on each rising or falling Clock edge. An
asynchronous Clear signal resets
regardless of the Clock signal.
clique A group of logic functions defined
as a single, named unit. The Compiler
attempts to keep clique members together
when it fits the project. A clique
assignment allows you to group all logic on
a speed-critical path, thus improving
performance.
If possible, all clique members are assigned
to the same LAB. If the clique members will
not fit into a single LAB, they are placed in
the same row (in FLEX 10K, FLEX 8000,
FLEX 6000, and MAX 9000 devices only) or
the same device.
Clock A signal that triggers registers.
In a flipflop or state machine, the Clock is
an edge-sensitive signal. The output of the
flipflop can change only on the Clock edge.
For example, in a D flipflop, the input
value is stored and placed on the output at
the Clock edge.
In some cases, MAX+PLUS II lists the Latch
Enable input to a latch as a Clock, e.g., in a
Delay Matrix timing analysis.
Clock Enable The level-sensitive signal on
an enabled flipflop, i.e., a flipflop with an
ÒEÓ suffix, including DFFE, TFFE, SRFFE,
and JKFFE. When the Clock Enable is low,
Clock transitions on the Clock input to the
flipflop are ignored.
column A vertical line of LABs connected
by a column FastTrack Interconnect path in
a FLEX 10K, FLEX 8000, FLEX 6000, or
MAX 9000 device.
COM or RS-232 port An RS-232 serial
communication port on a PC or UNIX
workstation. The BitBlaster, which is used
to configure and program devices in-
system, must connect to a COM port.
combinatorial feedback Feedback from a
logic cell that goes back into the deviceÕs
logic array. It is the direct function of the
inputs to a logic cell, and does not retain
values from earlier inputs.
combinatorial output Output from a logic
cell that is a direct function of the inputs,
without regard to the Clock; i.e., it does not
retain values resulting from earlier inputs.
81_GSBOOK.fm5 Page 302 Tuesday, October 14, 1997 4:04 PM