Unit installation

Glossary
Altera Corporation 301
Glossary
Glossary
Array Types in the IEEE Standard VHDL
Language Reference Manual for more
information. Only one- and two-
dimensional arrays of scalar elements are
supported.
In Verilog HDL, a bus is an array of nets,
and is limited to 256 symbolic names. See
section 3.3: Vectors in the IEEE Standard
Hardware Description Language Based on
the Verilog Hardware Description
Language manual for more information.
bus (or group) name The name of a bus (or
group) of up to 256 nodes.
A single-range or dual-range name consists
of up to 32 name characters, followed by
one or two ranges of numbers or arithmetic
expressions in brackets. (Dual-range
names are not supported in Waveform
Editor files.) The start and end of the
number range are separated by two
periods. Each number in the sequence
represents an individual node (or bit).
Example: bus a[4..1] consists of the
nodes a4, a3, a2, and a1.
Example: bus b[2..1][1..0] consists of
the nodes b2_1, b2_0, b1_1, and b1_0.
A sequential name, consisting of a comma-
separated list of names, can be entered in
AHDL Text Design Files (.tdf) and Graphic
Design Files (.gdf). In TDFs only, this list of
names must be enclosed in parentheses.
Sequential bus names can include single-
and dual-range bus names.
Example: a[3..0],dout[6..4],z3
The first name in the series of names in a
single-range, dual-range, or sequential
name is the most significant bit (MSB) of
the bus; the last name is the least significant
bit (LSB).
An arbitrary bus name, consisting of up to
32 name characters, can be entered in a
Waveform Design File (.wdf), Simulator
Channel File (.scf), or Vector File (.vec). An
arbitrary bus name does not indicate how
many members are included in the bus.
bus pinstub The location on the boundary
of a mega- or macrofunction symbol,
represented by an ÒxÓ in the Symbol File
(.sym), that represents multiple inputs or
outputs to the function. A bus (thick line)
drawn in a Graphic Editor file must
connect to a bus pinstub with the same
number of bits to be recognized as a
connection to the function.
ByteBlaster A Parallel download cable
that allows PC users to program and
configure devices in-system. The
ByteBlaster provides programming
support for MAX 7000S and MAX 9000
devices, and configuration support for
FLEX 6000, FLEX 8000, and FLEX 10K
devices. Multi-device JTAG chain
programming and configuration are also
available for FLEX 10K, MAX 7000S, and
MAX 9000 devices. Multi-device FLEX
chain configuration is available for
FLEX 6000, FLEX 8000, and FLEX 10K
devices.
The ByteBlaster is connected to a parallel
printer port on a PC via a fully populated
DB25-to-DB25 cable. The ByteBlasterÕs
10-pin female plug connects to a 10-pin
male header on the circuit.
81_GSBOOK.fm5 Page 301 Tuesday, October 14, 1997 4:04 PM