81_GSBOOK.fm5 Page 277 Tuesday, October 14, 1997 4:04 PM Appendix A MAX+PLUS II Command-Line Mode You can operate the MAX+PLUS II Compiler, Timing Analyzer, and Simulator from the command prompt under UNIX, Microsoft Windows NT, and Microsoft Windows 95.
81_GSBOOK.fm5 Page 278 Tuesday, October 14, 1997 4:04 PM MAX+PLUS II Getting Started To run MAX+PLUS II from a command prompt, type: maxplus2 -h | -v | { [ ] } 9 Multiple batch and I/O options can be used for a single project; multiple projects can be processed with the same command line. The indicates the end of the options for that project.
81_GSBOOK.fm5 Page 279 Tuesday, October 14, 1997 4:04 PM Appendix A: MAX+PLUS II Command-Line Mode The are shown below. For each option, the defaults to if you specify empty quotation marks (""). I/O Option: Action: -tao "" saves Timing Analyzer output in .tao; if this option is not used, .tao is generated automatically -scf "" uses .
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81_GSBOOK.fm5 Page 281 Tuesday, October 14, 1997 4:04 PM Appendix B Altera Support Services AlteraÕs support team is dedicated to resolving your technical issues quickly. Altera responds to your questions promptly and efficiently via telephone, fax, or e-mail. Applications Engineers are located at Altera headquarters in San Jose, California, and at locations around the world.
81_GSBOOK.fm5 Page 282 Tuesday, October 14, 1997 4:04 PM MAX+PLUS II Getting Started Contacting Altera Support Services Table B-1 describes AlteraÕs support services. Table B-1. Altera Support Services (Part 1 of 2) Support Service Product Information Contact Information Note (1) Tel: (408) 544-7104 E-mail: news@altera.com WWW: http://www.altera.com BBS: 544-6421 Note (2) FTP site: ftp@altera.
81_GSBOOK.fm5 Page 283 Tuesday, October 14, 1997 4:04 PM Appendix B: Altera Support Services Table B-1. Altera Support Services (Part 2 of 2) Support Service Technical Publications Contact Information Note (1) Tel: (888) 3-ALTERA E-mail: lit_req@altera.com WWW: http://www.altera.com BBS: 544-6421 Note (2) FTP site: ftp@altera.
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81_GSBOOK.fm5 Page 285 Tuesday, October 14, 1997 4:04 PM Appendix C Additional Workstation Configuration Information This section describes how to change additional workstation configuration items that control the appearance of MAX+PLUS II windows, serial port configuration, screen height and width, printer ports, and fonts. ■ ■ ■ ■ ■ Altera Corporation Customizing MAX+PLUS II Colors ..................................................... 286 Using the mwcolormanager Utility ..............................
81_GSBOOK.fm5 Page 286 Tuesday, October 14, 1997 4:04 PM MAX+PLUS II Getting Started Customizing MAX+PLUS II Colors You can customize the colors of various elements in the MAX+PLUS II window by editing the ASCII-format win.ini file, which is copied into the /windows directory the first time you run MAX+PLUS II. The settings in this file determine the colors of basic window elements when Windows Òlook and feelÓ is selected.
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81_GSBOOK.fm5 Page 288 Tuesday, October 14, 1997 4:04 PM MAX+PLUS II Getting Started 1 If the appearance of colors in MAX+PLUS II is not satisfactory, and editing the win.ini file does not help the problem, you should select the Windows Òlook and feel,Ó either by setting the MWLOOK environment variable described on page 290, or with the Change Look system menu.
81_GSBOOK.fm5 Page 289 Tuesday, October 14, 1997 4:04 PM Appendix C: Additional Workstation Configuration Information If you are using the Bourne or Korn Shell, environment variables are located in your .profile file, and have the following format: set = MAX2_HOME The MAX2_HOME variable specifies the name of the MAX+PLUS II home directory. The default is /usr/maxplus2.
81_GSBOOK.fm5 Page 290 Tuesday, October 14, 1997 4:04 PM MAX+PLUS II Getting Started Table C-1. Serial Ports Platform Name MWCOM1 MWCOM2 MWCOM3 MWCOM4 IBM RISC System/6000 /dev/tty0 /dev/tty1 /dev/tty1 /dev/tty1 SPARCstation running SunOS 4.1.3 /dev/ttya /dev/ttyb /dev/ttyc /dev/ttyd SPARCstation running Solaris 2.
81_GSBOOK.fm5 Page 291 Tuesday, October 14, 1997 4:04 PM Appendix C: Additional Workstation Configuration Information MWRGB_DB The MWRGB_DB variable specifies the full pathname to the file rgb.txt, which maps color names to 24-bit RGB color values in the X server. If MWRGB_DB is not used, the program looks for rgb.txt in the following directories, in order: 1. 2. 3. 4.
81_GSBOOK.fm5 Page 292 Tuesday, October 14, 1997 4:04 PM MAX+PLUS II Getting Started MWWM The MWWM variable determines which window manager is used on the system. MWWM may take the following values: Value: Effect: MWM OLWM TWM uses Motif as the window manager uses OpenLook as the window manager uses the standard X window manager MAX+PLUS II automatically detects whether you are using Motif or OpenLook. This variable should be used only if you are using the standard X window manager, TWM.
81_GSBOOK.fm5 Page 293 Tuesday, October 14, 1997 4:04 PM Appendix C: Additional Workstation Configuration Information 4. Type xset fp rehash 9 to reinitialize the font cache in the X server. 5. Depending on your operating system, perform one of the following: v For Solaris, HP-UX, and AIX with Common Desktop Environment (CDE) 1.0 (autostart enabled), go through the following steps: a. Add the line DTSOURCEPROFILE=true to the .dtprofile file in your home directory. b. Edit the .
81_GSBOOK.fm5 Page 294 Tuesday, October 14, 1997 4:04 PM MAX+PLUS II Getting Started Font Aliases The [FontSubstitutes] section of the win.ini file in the /windows directory provides aliases for font names. These aliases are used to bind the MAX+PLUS II font names to the font names available under the X server.
81_GSBOOK.fm5 Page 295 Tuesday, October 14, 1997 4:04 PM Appendix C: Additional Workstation Configuration Information [ports] lpt1:=lp -c "%s" lpt2:=lp -c -dps1700 "%s" lpt3:= ... The [ports] section lists the communication and printer ports available to MAX+PLUS II. The Windows LPTn: variables are equated to UNIX commands. In this example, LPT1 and LPT2 are equated to the print command lp. MAX+PLUS II prints its output to an intermediate Postscript file, which is then substituted for the term “%s”.
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81_GSBOOK.fm5 Page 297 Tuesday, October 14, 1997 4:04 PM Glossary This glossary defines selected terms used in MAX+PLUS II documentation. 1 Choose Glossary (Help menu) to view the full MAX+PLUS II glossary on-line. AHDL see Altera Hardware Description Language. ACF see Assignment & Configuration File. active-low node A node that is activated when it is assigned a value of zero (0 in AHDL and Verilog HDL or '0' in VHDL) or GND (e.g., clrn, prn, oen).
81_GSBOOK.fm5 Page 298 Tuesday, October 14, 1997 4:04 PM MAX+PLUS II Getting Started MAX+PLUS II Text Editor or any standard text editor, then compile, simulate, and program your projects within MAX+PLUS II. AHDL supports Boolean equation, state machine, conditional, and decode logic. AHDL also allows you to create and use parameterized functions, and includes full support for functions in the Library of Parameterized Modules (LPM). Text Design Export files (.tdx) and Text Design Output Files (.
81_GSBOOK.fm5 Page 299 Tuesday, October 14, 1997 4:04 PM Glossary area marquee In the Graphic or Symbol Editors, the rectangular boundary surrounding an area selection, which is created by dragging Button 1 with the Selection tool. In the Hierarchy Display, the rectangular border that is visible as you drag the mouse to select an area. The marquee is visible only while you are dragging the mouse. area selection A defined rectangular region that includes one or more adjacent objects.
81_GSBOOK.fm5 Page 300 Tuesday, October 14, 1997 4:04 PM MAX+PLUS II Getting Started MAX+PLUS II applications and commands are background processes: ■ ■ ■ ■ ■ ■ ■ Compiler Programmer Simulator Timing Analyzer ACF Reader Waveform Editor Import Vector File command (File menu) MAX+PLUS II Project Archive command (File menu) balloon text Pop-up text in the Floorplan Editor that provides information on an item under the mouse pointer, such as a pin, I/O cell, logic cell, embedded cell, or an assignment bin.
81_GSBOOK.fm5 Page 301 Tuesday, October 14, 1997 4:04 PM Glossary Array Types in the IEEE Standard VHDL Language Reference Manual for more information. Only one- and twodimensional arrays of scalar elements are supported. In Verilog HDL, a bus is an array of nets, and is limited to 256 symbolic names. See section 3.3: Vectors in the IEEE Standard Hardware Description Language Based on the Verilog Hardware Description Language manual for more information.
81_GSBOOK.fm5 Page 302 Tuesday, October 14, 1997 4:04 PM MAX+PLUS II Getting Started C chip A group of logic functions defined as a single, named unit. A chip is assigned to an actual device by either the user or the Compiler. You can make chip assignments on logic functions in design files. Items that are assigned to the same chip are placed in the same device during compilation.
81_GSBOOK.fm5 Page 303 Tuesday, October 14, 1997 4:04 PM Glossary Command File (.cmd) An ASCII text file (with the extension .cmd) that contains commands for batch-mode simulation. comment In the Graphic and Symbol Editors, a comment is a free-floating block of text used to document the design. It is not associated with any object. A comment stands alone anywhere within Graphic Editor files. A comment also stands alone within the symbol border of a Symbol Editor file.
81_GSBOOK.fm5 Page 304 Tuesday, October 14, 1997 4:04 PM MAX+PLUS II Getting Started D database A flattened representation of all design files in a MAX+PLUS II project hierarchy. The database is used internally by Compiler modules during compilation. decimal The base 10 number system (radix). Decimal digits are 0 through 9. In AHDL,VHDL, and Verilog HDL no special notation is needed to indicate decimal digits. default Simulator Channel File (.scf) A Simulator Channel File (.
81_GSBOOK.fm5 Page 305 Tuesday, October 14, 1997 4:04 PM Glossary FLEX 6000, FLEX 8000, and FLEX 10K device families. Altera also offers Configuration EPROM devices which are used to configure FLEX 6000, FLEX 8000, and FLEX 10K devices. device assignment A device assignment assigns a user-specified block of logic functions, called a chip, to a specific Altera device.
81_GSBOOK.fm5 Page 306 Tuesday, October 14, 1997 4:04 PM MAX+PLUS II Getting Started Dynamic models allow a simulation to run faster; however, the Compiler requires additional time to generate the SNF. E EAB EC see Embedded Array Block. see embedded cell. EDIF Electronic Design Interchange Format. An industry-standard format for the transmission of design data.
81_GSBOOK.fm5 Page 307 Tuesday, October 14, 1997 4:04 PM Glossary The EAB is fed by row interconnect paths and a dedicated input bus. embedded cell (EC) A memory element that exists in the embedded array of a FLEX 10K device, and which can implement memory (RAM or ROM) or combinatorial logic. An Embedded Array Block (EAB) consists of a group of 8 embedded cells that can implement a memory block of 256 × 8, 512 × 4, 1,024 × 2, or 2,048 × 1 bits.
81_GSBOOK.fm5 Page 308 Tuesday, October 14, 1997 4:04 PM MAX+PLUS II Getting Started fan-in and fan-out Fan-in refers to input signals that feed the input equations of a logic cell. Fan-out refers to output signals that are fed by the output equations of a logic cell. FastTrack Interconnect Dedicated connection paths that span the entire width and height of a FLEX 6000, FLEX 8000, MAX 9000, or FLEX 10K device.
81_GSBOOK.fm5 Page 309 Tuesday, October 14, 1997 4:04 PM Glossary You can also display a read-only version of Fit File information from the most recent project compilation in the Floorplan Editor. FLEX Chain File (.fcf) An ASCII file (with the extension .fcf) that stores programming file names for use in configuring multiple FLEX 6000, FLEX 8000, or FLEX 10K devices in a Passive Serial configuration scheme.
81_GSBOOK.fm5 Page 310 Tuesday, October 14, 1997 4:04 PM MAX+PLUS II Getting Started specify a required fMAX for an entire project and/or for any input pin (INPUT or INPUTC), bidirectional pin (BIDIR or BIDIRC input function), or a register. Function Prototype Specifies the ports (pinstubs) of a primitive, megafunction, or macrofunction in AHDL. A Function Prototype consists of the name of the function, and a list of its inputs and outputs.
81_GSBOOK.fm5 Page 311 Tuesday, October 14, 1997 4:04 PM Glossary ■ With the Global Signal logic option in the Individual Logic Options dialog box, which you can open from the Logic Options dialog box (Assign menu). When this option is turned on for an input pin or for a single-output logic function, it is equivalent to using a GLOBAL primitive. Turning this logic option off prevents an input pin from being used as a global signal. GND A low-level input voltage. Graphic Design File (.
81_GSBOOK.fm5 Page 312 Tuesday, October 14, 1997 4:04 PM MAX+PLUS II Getting Started In Graphic Design Files (.gdf) and Text Design Files (.tdf), hard logic primitives/ ports include INPUT, INPUTC, OUTPUT, OUTPUTC, BIDIR, BIDIRC, LCELL, MCELL, DFF, DFFE, TFF, TFFE,JKFF, JKFFE, SRFF, SRFFE, and LATCH. However, INPUT and INPUTC primitives that do not affect project outputs are not considered to be hard logic functions.
81_GSBOOK.fm5 Page 313 Tuesday, October 14, 1997 4:04 PM Glossary Hierarchy Interconnect File (.hif) An ASCII file (with the extension .hif) created by the CompilerÕs Netlist Extractor module. This file specifies the hierarchical interconnections between design files in a project. MAX 9000 device. I/O cells permit short setup time. History File (.hst) An ASCII file (with the extension .hst) created by the MAX+PLUS II Simulator.
81_GSBOOK.fm5 Page 314 Tuesday, October 14, 1997 4:04 PM MAX+PLUS II Getting Started Programmer. The Programmer also provides the capability to configure one or more FLEX 10K devices in a JTAG chain and one or more FLEX 6000, FLEX 8000, or FLEX 10K devices in a FLEX chain. in-system programmability (ISP) The capability of EEPROM-based devices, such as AlteraÕs MAX 9000 and MAX 7000S devices, to be programmed after they have been mounted on a printed circuit board.
81_GSBOOK.fm5 Page 315 Tuesday, October 14, 1997 4:04 PM Glossary Verilog HDL Module or Gate Instantiation, an instance is represented by the module or gate name, followed by the instance name. interactive mode The simulation mode in which you choose on-screen options and buttons, and execute menu commands, with the keyboard or mouse. ISP see in-system programmability. J JTAG boundary-scan testing Testing that isolates a deviceÕs internal circuitry from its I/O circuitry.
81_GSBOOK.fm5 Page 316 Tuesday, October 14, 1997 4:04 PM MAX+PLUS II Getting Started command (File menu) or Multi-Device JTAG Chain Setup command (JTAG menu). K keyword Words that are reserved for implementing syntax in files used as inputs to MAX+PLUS II, including AHDL Text Design Files (.tdf), Assignment & Configuration Files (.acf), Command Files (.cmd), EDIF Command Files (.edc), Library Mapping Files (.lmf), VHDL Design Files (.vhd), Verilog Design Files (.v) and Vector Files (.vec).
81_GSBOOK.fm5 Page 317 Tuesday, October 14, 1997 4:04 PM Glossary location A generic term that refers to an assignable physical resource in the interior of an Altera device.
81_GSBOOK.fm5 Page 318 Tuesday, October 14, 1997 4:04 PM MAX+PLUS II Getting Started column number of the LAB. In Classic, MAX 5000, and MAX 7000 devices, logic cells have numbers of the format LC, where may consist of both digits and letters. 1 FLEX 10K, FLEX 8000, and MAX 9000 devices have specialized logic cells, called I/O cells, on the periphery of the device. logic cell Turbo Bit see Turbo Bit. logic element see logic cell.
81_GSBOOK.fm5 Page 319 Tuesday, October 14, 1997 4:04 PM Glossary for the Normal style. To view the settings for a predefined style, open the Define Synthesis Style dialog box, select the style in the Style box, and choose the Use Default button. logical operator An operator that performs a logic operation on nodes, groups, or numbers. AHDL logical operators are NOT (!), AND (&), NAND (!&), OR (#), NOR (!#), XOR ($), and XNOR (!$). VHDL logical operators are AND, NAND, OR, NOR, XOR, and NOT.
81_GSBOOK.fm5 Page 320 Tuesday, October 14, 1997 4:04 PM MAX+PLUS II Getting Started logic cells, and multiple global Clocks with optional inversion. MAX 7000S devices also offer the additional capability of insystem programming via JTAG boundaryscan test circuitry. 1 Altera strongly recommends using MAX 7000S and MAX 7000E devices rather than equivalent MAX 7000 devices for new designs. MAX 9000 An Altera device family based on the third generation of Multiple Array MatriX architecture.
81_GSBOOK.fm5 Page 321 Tuesday, October 14, 1997 4:04 PM Glossary FLEX 10K, FLEX 8000, FLEX 6000, MAX 9000, and MAX 7000 device architectures. Altera MegaCore megafunctions consist of several different design files. A post-synthesis AHDL design file is used for design implementation (i.e., fitting) in the target Altera device. In addition, VHDL or Verilog HDL functional simulation models are supplied for design and debugging with standard EDA simulation tools.
81_GSBOOK.fm5 Page 322 Tuesday, October 14, 1997 4:04 PM MAX+PLUS II Getting Started the initial content of a memory block (RAM or ROM), i.e., the initial values for each address. This file is used during project compilation and/or simulation. Memory Initialization Output File (.mio) An ASCII file (with the extension .mio) that is generated when the Compiler creates a Text Design Export File (.tdo) for a project. A TDO File that implements RAM or ROM always has an MIO File for each memory segment.
81_GSBOOK.fm5 Page 323 Tuesday, October 14, 1997 4:04 PM Glossary embedded processor-type programming environments. Item: multi-level synthesis Logic synthesis that takes advantage of all available logic options, including all options listed in the Define Synthesis Style and Advanced Options dialog boxes (Assign menu). This type of logic synthesis can handle projects with extremely complex logic, without requiring user intervention to achieve a fit.
81_GSBOOK.fm5 Page 324 Tuesday, October 14, 1997 4:04 PM MAX+PLUS II Getting Started Item: Name Character Exception: 1 1. VHDL names No slash (/) or dash (-) is permitted. The name must start with a letter, cannot end with an underscore (_), and cannot contain two underscores (_ _) in a row. VHDL keywords cannot be used. ACF names Names that contain slash (/), dash (-), vertical bar (|), colon (:), and/or period (.) characters must be enclosed in double quotation marks ("). 2.
81_GSBOOK.fm5 Page 325 Tuesday, October 14, 1997 4:04 PM Glossary Type: Meaning: COMB Node or group is fed by combinatorial logic, e.g., an AND gate. Node or group is fed by a register (implemented with a logic cell on the device). Node is fed by a state machine. REG MACH Normal logic synthesis style The Alteraprovided style that directs the Logic Synthesizer to optimize your project for minimum silicon resource usage.
81_GSBOOK.fm5 Page 326 Tuesday, October 14, 1997 4:04 PM MAX+PLUS II Getting Started comprise a Òone-hotÓ code sample because in each of these four values a single bit is set to 1. You can manually implement one-hot encoding. In addition, the Global Project Logic Synthesis command (Assign menu) includes a One-Hot State Machine Encoding option to allow the Compiler to automatically implement one-hot encoding for the entire project.
81_GSBOOK.fm5 Page 327 Tuesday, October 14, 1997 4:04 PM Glossary such as the functions in the Library of Parameterized Modules (LPM), are inherently parameterized and require parameter values to be assigned. represented as a node with an input, output, or bidirectional I/O type and a pin input, registered, or combinatorial node type. Parameters can be assigned to any individual instance of a megafunction in MAX+PLUS II to control its size or implementation.
81_GSBOOK.fm5 Page 328 Tuesday, October 14, 1997 4:04 PM MAX+PLUS II Getting Started Declarations, Module Instantiations, and Gate Instantiations of Verilog Design Files (.v). PLS-ES development systems include the following MAX+PLUS II applications and features: pinstub name A symbolic name that identifies an input or output of a logic function. ■ ■ ■ In the Symbol Editor, the ÒvisibleÓ pinstub name appears both inside and outside of the symbol.
81_GSBOOK.fm5 Page 329 Tuesday, October 14, 1997 4:04 PM Glossary Instantiation, its ports are connected to signals with Port Map Aspects. In Verilog HDL, a port in a Module Declaration represents an input or output of the current file. When an instance of a lower-level design file is implemented with a Module Instantiation, its ports are connected by order or by name to the Module Declaration ports of the module being instantiated.
81_GSBOOK.fm5 Page 330 Tuesday, October 14, 1997 4:04 PM MAX+PLUS II Getting Started Programmer Log File (.plf) An ASCII file (with the extension .plf) generated by the Programmer that records programming session commands and messages. Programmer Object File (.pof) A binary file (with the extension .pof) generated by the CompilerÕs Assembler module. This file contains the data used by the MAX+PLUS II Programmer to program an Altera device.
81_GSBOOK.fm5 Page 331 Tuesday, October 14, 1997 4:04 PM Glossary Example: group a[2..0] consists of the nodes a2, a1, and a0; the MSB is a2; and the LSB is a0. registered output The output of a flipflop or latch, which can feed an output pin on the device. Raw Binary File (.rbf) A binary file (with the extension .rbf) containing configuration data for FLEX 6000, FLEX 8000, and FLEX 10K devices. This file is the binary equivalent of a Tabular Text File (.ttf).
81_GSBOOK.fm5 Page 332 Tuesday, October 14, 1997 4:04 PM MAX+PLUS II Getting Started resource assignment An assignment of a logic function in a project to a particular pin, logic cell, I/O cell, embedded cell, logic array block (LAB), embedded array block (EAB), row, column, or chip. This type of resource assignment assigns a logic function to a physical resource in a device.
81_GSBOOK.fm5 Page 333 Tuesday, October 14, 1997 4:04 PM Glossary On an asynchronous RAM block, the setup time is the minimum time interval between the application of a signal at the input pin that feeds the data or address inputs and a low-to-high or high-to-low transition at the input pin that feeds the Write Enable input of the RAM block. Internal setup times for flipflops, latches, and asynchronous RAM, which are not user-defined, similarly constrain signals that are generated within the device.
81_GSBOOK.fm5 Page 334 Tuesday, October 14, 1997 4:04 PM MAX+PLUS II Getting Started separated by two periods. Each number in the sequence represents an individual node (or Òbus bitÓ). The identifier cannot end with a digit. Example: group a[4..1] consists of the nodes a4, a3, a2, and a1. In a Graphic Editor files, a sequential bus name can also include one or more singlerange bus names in a series.
81_GSBOOK.fm5 Page 335 Tuesday, October 14, 1997 4:04 PM Glossary state machine A sequential circuit that advances through a number of states. A state machine can be defined in a Waveform Design File (.wdf), State Machine File (.smf), Vector File (.vec), VHDL Design File (.vhd), Verilog Design File (.v) or in a State Machine Declaration in an AHDL Text Design File (.tdf). sub-project see super-project. subdesign A lower-level design file in a MAX+PLUS II project, i.e.
81_GSBOOK.fm5 Page 336 Tuesday, October 14, 1997 4:04 PM MAX+PLUS II Getting Started 1 In the UNIX workstation environment, filenames and hence subdesign names are case-sensitive. sum-of-products A Boolean expression is said to be in sum-of-products form if it consists of product terms combined with the OR operator. ID numbers to nodes when the project is compiled.
81_GSBOOK.fm5 Page 337 Tuesday, October 14, 1997 4:04 PM MAX+PLUS II Getting Started clocks the register. This time always represents an external pin-to-pin delay. tCO is also a timing assignment that specifies the maximum acceptable Clock to output delay. In MAX+PLUS II, you can specify a required tCO for an entire project and/or for any input pin (INPUT or INPUTC), output pin (OUTPUT or OUTPUTC), or TRI buffer (i.e., BIDIR or BIDIRC pin output function) pin. TDF see Text Design File.
81_GSBOOK.fm5 Page 338 Tuesday, October 14, 1997 4:04 PM MAX+PLUS II Getting Started timing analysis displayed in the MAX+PLUS II Timing Analyzer. timing assignment An assignment that specifies desired speed performance on one or more logic functions. The tPD, tSU, tCO, and fMAX timing assignments, as well as Òtiming cuts,Ó are available. You can assign timing to individual logic functions and specify default timing for the project as a whole.
81_GSBOOK.fm5 Page 339 Tuesday, October 14, 1997 4:04 PM MAX+PLUS II Getting Started .
81_GSBOOK.fm5 Page 340 Tuesday, October 14, 1997 4:04 PM MAX+PLUS II Getting Started Simulator uses vectors to simulate the behavior of the project; the Programmer and Simulator use vectors for functional testing. Vectors for simulation and functional can be defined in Vector Files (.vec) or Simulator Channel Files (.scf). Functional testing vectors can also be stored in programming files. Vectors for design entry can be defined in a Waveform Design File (.wdf). Vector File (.
81_GSBOOK.fm5 Page 341 Tuesday, October 14, 1997 4:04 PM MAX+PLUS II Getting Started VHDL Memory Model Output File (.vmo) A Compiler-generated VHDL standard netlist file (with the extension .vmo) that contains VHDL simulation models. The Compiler automatically generates a VHDL Memory Model Output File for the project when it generates an EDIF Output File (.edo) that contains one or more RAM or ROM blocks. include state machines with waveforms that represent different state names.
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Index Nonalphabetic .cshrc file 26, 28, 30, 32, 68, 288 .profile file 68, 288 .xinitrc file 288 /usr/lib/x11/fonts directory 292 /usr/max2work directory see max2work directory /usr/maxplus2 directory see maxplus2 directory /windows directory 294 \lit directory xvii, xviii, 51 Numerics 8count macrofunction 173 A A+PLUS 95 About MAX+PLUS II command 92 ACF 97, 109, 115, 130, 135, 234 adapters installing 58 releasing 59 adders 118 ADF 95, 96, 129 Adobe Acrobat Reader 51 AHDL auto_max.
MAX+PLUS II Getting Started BitBlaster baud rate dipswitch settings 63 capabilities 150 installation 61 bldfamily utility 292 BNF see Backus-Naur Form Boolean equations (AHDL) 190 branch buttons 126 breakpoints 145 bulletin board service (BBS) 282, 283 bus lines 181 buses connecting 104, 182 creating 112 naming 182 Button 2 menus 102, 161 ByteBlaster capabilities 150 installation 65 Windows NT driver installation 11 C CD-ROM mounting 16 running help from the CD-ROM 19 unmounting 25 chip assignments 98 chi
Index Design Doctor Settings command 219 Design Doctor utility 138, 219 design entry, general description 95 design evaluations 282 design file definition 86 Device command 217 Device Model File (.
MAX+PLUS II Getting Started Font commands 182, 188, 215 font.dir file 292 fonts, UNIX workstation 291, 292, 295 FTP site 282, 283 Function Prototypes 118 functional simulation 143 Functional SNF Extractor module 136 functional testing 111, 145, 154 G GDF 96, 129, 168, 210 glitch monitoring 145 Global Project Device Options command 220 Global Project Logic Synthesis command 220 global signals 100 Glossary button 92 Glossary command 91 GND pins 115 Golden Rules command 90 Graphic Design File (.
Index installation, PC see also network licensing Adobe Acrobat Reader 51 BitBlaster installation 61 ByteBlaster installation 65 determining free disk space 7 file organization 69 FLEX Download Cable installation 60 Master Programming Unit installation 53 MegaCore/AMPP authorization codes 49 NEC 9801 steps 13 read.
MAX+PLUS II Getting Started Literature Department 283 lmdown utility 42 LMF 109, 133 lmgrd daemon 4, 34, 36, 37, 39, 40 lmhostid utility 45 lmremove utility 43 lmreread utility 44 lmstat utility 41 lmver utility 45 local routing assignments 98 local.options file 39 Locate All button 271 Locate button 226, 272 location assignments 98 Log File (.
Index Message Text File (.
MAX+PLUS II Getting Started P palette tools Graphic Editor 104, 171, 179 Waveform Editor 202 parallel port 150 parameter assignments 100 parameters default values 107 in AHDL 118 in macrofunctions 124 in megafunctions 124 Partitioner module 134 Partitioner/Fitter Status dialog box 224 PC installation see installation, PC PDF files xvii, 51 pins assignments 98 entering 176 naming 177 pinstubs 107 PLE3-12A programming unit 57 PLF 154 PL-MPU programming unit 57 POF 137, 153, 273 pop-up menus 102, 161 Portable
Index reserved pins 115 rgb.txt file 291 ripple clocks 138 ROM initialization 145 routing information 115, 237, 240 Routing Statistics command 239 RPT file 115, 130, 135, 222, 228 RS-232 port 289 rubberbanding 104 Rubberbanding command 174 S SAM (HP) 29 SAM+PLUS 95 sample files xxiv Save As command 169 SBF 138, 153 SCF 111, 143, 146, 154, 245, 265 SCH file 96, 104, 129 SDF Output File (.
MAX+PLUS II Getting Started Symbol File (.sym) 101, 106, 130, 184 symbol ID number 177 symbols connecting 179 creating 184 entering 172 flipping & rotating 105 moving 176 updating 104 syntax coloring 109, 117, 119, 122 Syntax Coloring command 186 System Administration Manager (SAM) (HP) 29 system requirements PC 6 UNIX workstation 14 system.ini file 13 T Tab Stops command 188, 193 Table File (.tbl) 112, 143, 260, 263 Tabular Text File (.
Index tutorial (continued) Timing Analyzer session 266 Waveform Editor sessions 196, 245, 261 virus-detection software 8 visible pinstub names 107 VO file 136, 137 vsafe.com 8 U W UNIX workstation installation see installation, UNIX workstation 14 /usr/lib/x11/fonts directory 292 /usr/max2work directory see max2work directory /usr/maxplus2 directory see maxplus2 directory V V file 108, 121, 129 Variable Section 189 VCC pins 115 Vector File (.vec) 109, 143, 146, 154 Verilog Design File (.
