Specifications

Chapter 3 Hardware
ReadyBoard 800 Reference Manual 27
Pin # Signal Input/
Output
Description
49 (B19) C/BE3* T/S
PCI Bus Command/Byte Enable 3 – See Pin 4 for more
information.
50 (B20) AD26 T/S PCI Address and Data Bus Line 26 – See Pin 3 for more
information.
51 (B21) +5V +5.0 volts ±5%
52 (B22) AD30 T/S PCI Address and Data Bus Line 30 – See Pin 3 for more
information.
53 (B23) GND Ground
54 (B24) REQ2* T/S
Bus Request 2 – This signal indicates a device desires use of the
bus sent to the arbitrator. This request line is not available when
the MiniModule ISA board is used. See Notes.
55 (B25) VI/O +5 volts – Reference voltage
56 (B26) CLK0 In PCI clock 0 – See Pin 27 for more information
57 (B27) +5V +5.0 volts ±5%
58 (B28) INTD* O/D
Interrupt D – This signal is used to request interrupts only for
multi-function devices.
59 (B29) INTA* O/D Interrupt A – This signal is used to request an interrupt.
60 (B30) NC Not connected (Reserved)
61 (C1) +5V +5.0 volts ±5%
62 (C2) AD01 T/S
PCI Address and Data Bus Line 1 – See Pin 3 for more
information.
63 (C3) AD04 T/S PCI Address and Data Bus Lines 4 – See Pin 3 for more
information.
64 (C4) GND Ground
65 (C5) AD08 T/S PCI Address and Data Bus Line 8 – See Pin 3 for more
information.
66 (C6) AD10 T/S PCI Address and Data Bus Line 10 – See Pin 3 for more
information.
67 (C7) GND Ground
68 (C8) AD15 T/S PCI Address and Data Bus Line 15 – See Pin 3 for more
information.
69 (C9) NC Not connected (SB0* – Snoop Backoff)
70 (C10) +3.3V +3.3 volts ±5%
71 (C11) LOCK* S/T/S
Lock – This signal indicates an operation that may require
multiple transactions to complete
72 (C12) GND Ground
73 (C13) IRDY* S/T/S
Initiator Ready – This signal indicates the master’s ability to
complete the current data cycle of the transaction
74 (C14) +3.3V +3.3 volts ±5%
75 (C15) AD17 T/S
PCI Address and Data Bus Line 17 – See Pin 3 for more
information.
76 (C16) GND Ground