Specifications
Chapter 3 Hardware
ReadyBoard 800 Reference Manual 25
PCI-104 Interface (J3)
The PCI-104 expansion interface uses a 120-pin (30x4) 2 mm connector. This connector carries all of
the appropriate PCI signals operating at clock speeds up to 33 MHz. The I/O Hub (82801DBM),
integrates a PCI arbiter that supports up to four devices with three external PCI masters. This interface
header accepts stackable modules and is located on the top of the board.
Table 3-4 provides the PCI-104 pins/signals and descriptions for 120-pins, 4 individual rows,
consecutive order (B1, A1, C1, D1), with 2 mm pin spacing.
Table 3-4. PCI-104 Pin/Signal Descriptions (J3)
Pin # Signal Input/
Output
Description
1 (A1) Key/GND Key - Ground
2 (A2) VI/O +5 volts – Reference voltage
3 (A3) AD05 T/S
PCI Address and Data Bus Line 5 – These address and data signal
lines (0-31) are multiplexed. A bus transaction consists of an
address followed by one or more data cycles.
4 (A4) C/BE0* T/S
PCI Bus Command/Byte Enable 0 – This signal line is one of four
signal lines. These signal lines are multiplexed, so that during the
address cycle, the command is defined and during the data cycle,
the byte enable is defined.
5 (A5) GND Ground
6 (A6) AD11 T/S
PCI Address and Data Bus Line 11 – See Pin 3 for more
information.
7 (A7) AD14 T/S PCI Address and Data Bus Line 14 – See Pin 3 for more
information.
8 (A8) +3.3V +3.3 volts ±5%
9 (A9) SERR* O/D System Error – This signal is for reporting address parity errors.
10 (A10) GND Ground
11 (A11) STOP* S/T/S Stop – This signal indicates the current selected device is
requesting the master to stop the current transaction
12 (A12) +3.3V +3.3 volts ±5%
13 (A13) FRAME* S/T/S PCI Bus Frame access – This signal is driven by the current master
to indicate the start of a transaction and will remain active until the
final data cycle
14 (A14) GND Ground
15 (A15) AD18 T/S PCI Address and Data Bus Line 18 – See Pin 3 for more
information.
16 (A16) AD21 T/S PCI Address and Data Bus Line 21 – See Pin 3 for more
information.
17 (A17) +3.3V +3.3 volts ±5%
18 (A18) IDSEL0 In Initialization Device Select 0 – This signal line is one of four signal
lines and are used as the chip-select signals during configuration.
19 (A19) AD24 T/S PCI Address and Data Bus Line 24 – See Pin 3 for more
information.
20 (A20) GND Ground