Specifications

Chapter 3 Hardware
ReadyBoard 800 Reference Manual 33
Pin # Signal Description
25, 26 CD2, CD1 Card Detect 1 & 2 – Connected through 100k ohm resister to +5 VDC, when
no CF card installed. A low (ground) on either pin causes an Or Gate to switch
placing VCC on CF voltage pins. Refer to pins -13, -36, -38.
27 SDD11 Secondary Disk Data 11 – Refer to SDD3 on pin-2 for more information.
28 SDD12 Secondary Disk Data 12 – Refer to SDD3 on pin-2 for more information.
29 SDD13 Secondary Disk Data 13 – Refer to SDD3 on pin-2 for more information.
30 SDD14 Secondary Disk Data 14 – Refer to SDD3 on pin-2 for more information.
31 SDD15 Secondary Disk Data 15 – Refer to SDD3 on pin-2 for more information.
32 SDCS3* Secondary Chip Select 3 – This signal, along with SDCS1*, selects the
compact flash card and indicates to the card when a byte or word operation is
being performed. This signal always accesses the odd byte of the word.
33, 40 NC Not Connected (VS1*, VS2*)
34 SDIOR*
Secondary Device I/O Read/Write Strobe – This signal is generated by the host
and gates the I/O data onto the bus from the compact flash card when the card
is configured to use the I/O interface.
35 SDIOW*
Secondary Device I/O Read/Write Strobe – This signal is generated by the host,
and clocks the I/O data onto the Card Data bus into the compact flash card
controller registers when the card is configured to use the I/O interface. The
clock occurs on the negative to positive edge of the signal (trailing edge).
36, 38 VCC Voltage Pin – Refer to pin-13 for more information.
37 IRQ15 Interrupt Request 15 – IRQ 15 is asserted by drive (CF) when it has a pending
interrupt (PIO transfer of data to or from the drive to the host).
39 MASTER* Master/Slave – This pin determines the Master or Slave configuration of the
compact flash by the jumper (JP3) setting. When this pin is grounded (jumper
inserted), this device is configured as Master. When this pin is open (jumper
removed), this device is configured as Slave (Default).
41 IDERST* Secondary IDE Reset – This input signal is the active low hardware reset from
the host. If this pin goes high, it is used as the reset signal. This pin is driven
high at power-up, causing a reset, and if left high will cause another reset.
42 SDIORDY
Secondary Device I/O-DMA Channel Ready – When negated, extends the host
transfer cycle of any host register access when the drive is not ready to respond
to a data transfer request. High impedance if asserted.
43 SDREQ
Secondary DMA Request – Used for DMA data transfers between the host
and device.
44 SDDACK* Secondary DMA Acknowledge – Asserted by host in response to DMA
request to initiate DMA transfers.
45 IDE LED2 IDE Activity – Indicates CF activity to yellow IDE LED (D5) on board edge.
46 CF2 CF2 (UDMA 33/66 Sense) – Senses the DMA mode for the compact flash.
47 SDD8 Secondary Disk Data 8 – Refer to SDD3 on pin-2 for more information.
48 SDD9 Secondary Disk Data 9 – Refer to SDD3 on pin-2 for more information.
49 SDD10 Secondary Disk Data 10 – Refer to SDD3 on pin-2 for more information.
50 GND Ground
Notes: The shaded area denotes power or ground. The signals marked with * = Negative true logic.