Specifications

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n It is used to operate the “A20 Gate” and 80286 CPU reset which are associated with
system protected mode control, as on other AT compatible computers;
n It provides several control signals for Little Board/286 onboard logic control, including:
CPU and bus speed control; EEPROM device control; serial port enables; printer port
enable; byte-wide socket enables; mono/color jumper sensing; keyboard disable switch
sensing.
4.3.9 Speaker Interface
One of the board's ASIC devices (U28) provides the logic for a PC compatible speaker port. The
speaker logic signal is buffered by a transistor amplifier, and provides approximately .1 watt of
audio power to an external 8 ohm speaker.
As in the standard PC, the speaker circuit's output frequency is based on two control signals: the
output of Timer 2; and the programming of two bits, 0 and 1, in I/O port 61h. Bit 1 of I/O port
61h is one term of a 2-input AND gate in ASIC U28, the other term being the output from Timer
2. Thus, setting bit 1 to a logic 1 enables the output of Timer 2 to the speaker, and a logic 0
disables it. If Timer 2 is disabled (by setting bit 0 of port 61h to a 0), then bit 1 of port 61h can be
used to control the speaker directly.
4.3.10 Battery-Backed Clock
An AT compatible date/time clock is located within the device at location U29. The device also
contains a CMOS static RAM, compatible with that in standard AT's, with the exception of the
added Watch Dog Timer function. System configuration data is normally stored in the clock
chip's CMOS RAM in a manner consistent with the convention used in other AT compatible
computers.
The battery-backed clock can be set using the SETUP. The CMOS RAM within the clock chip is
also initialized, along with the board's configuration EEPROM, using SETUP.
One unique feature of the board's battery-backed clock device is that it contains the backup battery
directly within the device! The battery is rated for a minimum of 10 years of clock and internal
CMOS RAM backup under conditions of no power to the board. Extra large soldering "pads"
have been used for the clock chip's pins, to make it easy to replace the device when the battery is
exhausted.
4.3.11 AT Expansion Bus
An I/O channel compatible with the standard AT Expansion Bus is provided on a pair of dual-row
header connectors labeled "J9" and "J10" on the board. J9 is a 64-pin header which contains a PC
Expansion Bus plus two added grounds, while J10 is a 40-pin header which carries the added
signals that distinguish the AT bus from the PC bus, plus four extra grounds. The signals to the
AT Expansion Bus are buffered, and offer approximately 24 mA of output drive current. Signal
levels are TTL compatible (inputs and outputs).
The PC bus signals on J9 include an 8-bit bi-directional data bus, 20 address lines, 6 levels of
interrupt, three DMA channel handshake lines, a number of other control lines, and power and
ground for expansion cards. The first 62 pins of J9 (A1-31, B1-31) correspond to the standard
signals on the 62-pin PC bus edgecard backplane; the last two pins of J9 carry extra