Specifications

4 - 10
DMA Transfer Speed
The board's DMA controller operates at one-half the CPU speed. Therefore, the DMA controller
clock rate is 8 MHz on 16 MHz boards, and 6 MHz on 12 MHz boards. This results in a clock
cycle time of either 167 (12 MHz boards) or 125 nS (16 MHz boards). In the AT architecture,
DRAM refresh is controlled over the CPU/memory bus. For this reason, all DMA data transfers
are generally done using the controller's byte mode, so that the required refresh cycles can occur.
Consequently, the DMA throughput rate in the AT architecture is limited by both the current
activity of the CPU and by the bus transfer latency.
All DMA bus transactions require 5 clock cycles. Adding 2.5 clock cycles for the DMA controller
to acquire the bus, and 1.5 cycles for the CPU to regain control of the bus, results in a requirement
of 9 clock cycles per DMA data cycle (8 or 16 bits). At 16 MHz, the DMA transfer rate is
therefore .89 mega-transfers per second (MT/S), and at 12 MHz it is .67 MT/S. However, there is
also a constant DRAM refresh rate that reduces these numbers by approximately 5%, to .84 MT/S
(16 MHz) and .63 MT/S (12 MHz). If the transfers are 16 bits, these numbers become: 1.6
megabytes/sec (16 MHz) and 1.2 megabytes/sec (12 MHz). 8-bit transfers result in half the
throughput.
4.3.7 Programmable Timers
An 8254 compatible timer/counter device is also included in the board's ASIC devices. This
device is utilized in the same manner as in a standard AT implementation. Each channel of the
8254 is driven by a 1.190 MHz clock, derived from a 14.318 MHz oscillator, which can be
internally divided down to provide a variety of frequencies.
The standard use of this device's timers is summarized in Table 4-5. Timer 3 can also be used as a
general purpose timer if the speaker function is not required.
Table 4-5. Timer Assignment
TIMER FUNCTION
0
1
2
ROM-BIOS clock tick (18.2 Hz)
DRAM refresh request timing (15 uS)
Speaker tone generation time base
4.3.8 Keyboard Interface
A mask programmed microcontroller (U31) functions as an AT compatible keyboard controller.
The port supports standard AT keyboards. The keyboard is generally connected by means of a
four-wire cable consisting of +5 volts, ground, and two bi-directional signal lines, one for data and
one for clock.
A keyboard need not be connected to this port for the system to operate. A flag in the system
configuration CMOS NOVRAM (in the battery-backed clock device) can be set so that the ROM-
BIOS power on self test will not halt if a keyboard is not present.
Besides generating the keyboard interface, the keyboard controller contains a digital I/O port
which is used for a variety of system functions: