Specifications

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The CPU and bus half-speed options are controlled by the ROM-BIOS SETUP utility and
SETSPEED program, which is included on the Little Board/286 Utilities diskettes. Refer to
Chapter 3 for further details. The expansion bus speed parameter in the board's Configuration
Memory is set to half-speed operation at the factory.
4.3.3 ROM-BIOS Sockets
A pair of EPROM sockets (U10,U11) with 16-bit wide data access normally contains the board's
AT compatible ROM-BIOS. Each socket is intended for use with a 27C256 EPROM (or
equivalent) device. The "high" (odd) data byte EPROM goes in U10, and the "low" (even) byte
goes in U11.
The board's wait state control logic automatically inserts four memory wait states in all CPU
accesses to these sockets. The ROM-BIOS sockets occupy the memory area from F0000h through
FFFFFh.
4.3.4 Onboard DRAM Memory
The board has four positions (U1-4) for "SIMM" DRAM modules each of which provides either
256K X 9 bits or 1M X 9 bits of system RAM. The onboard DRAM memory occupies the bottom
of the 80286's 16 megabyte memory space, beginning at 00000h.
The ninth bit of each DRAM module is used to generate a RAM parity bit, and the board's ASIC
devices generate or check RAM parity on each memory write or read. If a parity error is detected,
an NMI interrupt is generated, and the system software then determines what corrective action is
to be taken.
Either two or four onboard DRAM modules must be installed for the board to function.
Configuration jumpers indicate the number of DRAM memory modules present (two or four).
Additional system RAM, up to a maximum of 16 megabytes, can be installed on the AT
Expansion Bus.
A jumper option offers the feature of converting RAM memory beyond 640K bytes into what is
termed extended memory. With the extended memory option enabled, 640K bytes of the board's
DRAM is present in the normal 80286 system address space, and the balance of the memory
installed on the board is accessed in the extended address range beginning at 100000h. This
extended memory can be accessed by means of a number of available application and utility
programs, including both cache and RAM-disk drivers. Special programming techniques must be
used when writing software which accesses extended memory.
DRAM refresh is accomplished in the standard manner, with a 15 uS time base generated by
Timer 1. Refresh addresses are generated by one of the board's ASIC devices, and a REFRESH
signal on the AT Expansion Bus accommodates expansion cards plugged into the bus.