ReadyBoard 700 Single Board Computer Reference Manual P/N 5001722A Revision C
Notice Page NOTICE No part of this document may be reproduced, transmitted, transcribed, stored in a retrieval system, or translated into any language or computer language, in any form or by any means, electronic, mechanical, magnetic, optical, chemical, manual, or otherwise, without the prior written permission of Ampro Computers, Incorporated.
Contents Chapter 1 About This Manual .........................................................................................................1 Purpose of this Manual .......................................................................................................................1 Reference Material .............................................................................................................................1 Related Ampro Products .......................................................
Contents LCD Interface (J9)........................................................................................................................ 47 LVDS Interface (J7) ..................................................................................................................... 48 Miscellaneous................................................................................................................................... 49 Utility Interface (J18) ...............................................
Contents Figure B-1. PXE Agent Boot Setup Screen.....................................................................................77 List of Tables Table 2-1. Major Integrated Circuit Description and Function.........................................................10 Table 2-2. Connector Descriptions ..................................................................................................11 Table 2-3. Reset Switch (SW1) ...........................................................................
Contents vi Reference Manual ReadyBoard 700
Chapter 1 About This Manual Purpose of this Manual This manual is for designers of systems based on the ReadyBoard™ 700 single board computer (SBC). This manual contains information that permits designers to create an embedded system based on specific design requirements.
Chapter 1 About This Manual Chip specifications used on the ReadyBoard 700: • Intel Corporation and the Celeron or Pentium III processor used for the embedded CPU. Web site: http://www.intel.com/design/intarch/datashts/273299.htm = Pentium III Web site: http://www.intel.com/design/intarch/datashts/273509.htm = Celeron • VIA Technologies, Inc. and the Twister-T chipset, VT8606 and VT82C686B, used for the Northbridge/Video controller and Southbridge respectively. Web site: http://www.viatech.
Chapter 1 About This Manual • LittleBoard Family – These high-performance, highly integrated single-board computers use the EBX form factor (5.75x8.00 inches), and are available with Pentium III and Celeron processors. The EBX-compliant Little Board single-board computers offer functions equivalent to a complete laptop or desktop PC system, plus several expansion cards.
Chapter 1 4 About This Manual Reference Manual ReadyBoard 700
Chapter 2 Product Overview This introduction presents general information about the EPIC Architecture and the ReadyBoard 700 single board computer (SBC).
Chapter 2 Product Overview Product Description The ReadyBoard 700 is a mid-sized, EPIC-compatible, low cost, high quality single-board system, which contains all the component subsystems of a PC/AT PCI motherboard plus the equivalent of up to 5 PCI expansion boards. The ReadyBoard 700 is based on either the ultra high performance, highintegration 933MHz Low Voltage Pentium® III processor, or the Low- Voltage 650MHz Celeron processor, or the low cost, Ultra Low-Voltage 400MHz Celeron processor.
Chapter 2 Product Overview ♦ Supports dual bus master mode ♦ Supports Ultra DMA 33/66/100 modes ♦ Supports ATAPI and DVD peripherals ♦ Supports IDE native and ATA compatibility modes ♦ CompactFlash Adapter (Secondary IDE only) • Supports Type I or Type II PC Card socket • Supports IDE CompactFlash Card • Supports secondary IDE bus with Master/Slave jumper • Supports bootable CompactFlash card • Floppy/Parallel Interface ♦ Shared floppy/parallel connector ♦ Supports one standard (34-pin)
Chapter 2 Product Overview ♦ Supports PS/2 mouse ♦ Provides a shared over-current fuse • Audio interface ♦ Supports AC’97 standard ♦ AC’97 CODEC on board ♦ Supports Stereo Line In/Out ♦ Supports MIC in (Mono) • Ethernet Interface ♦ Supports two fully independent Ethernet (RJ45) ports ♦ Integrated LEDs on each port (Link/Activity and Speed) ♦ Two Intel 82551ER Controller chips ♦ Supports IEEE 802.
Chapter 2 Product Overview Block Diagram Figure 2-2 shows the functional components of the board. Intel CPU Clock CRT VGA Northbridge VT8606 Memory Bus LVDS LCD PC/104-Plus Bus Connector Ethernet Controller 82251ER Ethernet Controller 82251ER SDRAM SODIMM Temp SMBus PCI Bus ATA Southbridge VT82C686B IDE Primary IDE Secondary CompactFlash Socket IrDA 1.
Chapter 2 Product Overview Major Integrated Circuits (ICs) Table 2-1 lists the major integrated circuits, including a brief description of each, on the ReadyBoard 700 and Figure 2-3 shows the location of the major chips. Table 2-1. Major Integrated Circuit Description and Function Chip Type CPU (U4) Intel Mfg. Model Pentium III or Celeron Northbridge (U7) VIA VT8606 Technologies, Inc. (Twister-T) Southbridge (U10) VIA VT82C686B Southbridge (provides most standard I/O Technologies, Inc.
Chapter 2 Product Overview Connector Definitions Table 2-2 describes the connectors shown in Figures 2-3 to 2-5. All I/O connectors use 0.1” pin spacing unless otherwise indicated. Table 2-2. Connector Descriptions Jack # Signal/Device Description BTI RTC battery (B1) 2-pin, 1.25 header for battery input DIMM1 SODIMM 144-pin socket for SDRAM SODIMM J1 Fan connector 3-pin header provides +12v, tach, and ground to fan.
Chapter 2 Product Overview Serial B (J3) (COM3 & 4) Fan (J1) GPIO (J2) J1 J3 4 3 U2 Q11 J4 1 JP6 2 Serial A (J5A/B) (COM1 & 2) U12 U1 J2 Power In (J4) JP1 U32 J5 U3 U4 LVDS (J7) Power-On Header (J6) J6 J26 D1 JP2 Y1 J7 CRT (J8) (VGA) U5 J8 U6 LCD (J9) U33 J13 J9 U7 U8 J12 Ethernet 1 (J10) J10 PC/104-Plus (J12) J14 PC/104 (J13A/B J14A/B) Y2 J11 Ethernet 2 (J11) Y3 U10 U11 J16 D2 J19 J18 SW1 X2 Utility (J18) U13 D4 J20 J21 Audio In/ Out (J19) USB 2 & 3
D12 U26 Q10 Q8 U25 D11 Q9 RB700_02aa U28 L1 U27 Product Overview U29 Chapter 2 Q6 D10 U24 U23 Q7 Q5 D9 SODIMM Socket (DIMM1) U22 CompactFlash Socket (J23) U21 DIMM1 USB 1 Fuse (F4) F4 F3 U20 USB 0 Fuse (F3) J23 Keyboard/ Mouse Fuse (F2) F1 USB 2 & 3 Fuse (F1) D8 F2 Q4 Q3 D7 U19 U16 U17 D5 Q2 D6 Figure 2-5. Connector and Component Locations (Bottom view) NOTE Pin-1 is shown as a black square in all connectors and jumpers in all illustrations.
Chapter 2 Product Overview Jumper Definitions Table 2-5 describes the jumpers shown in Figure 2-6. Refer to the Oops! Jumper to clear the BIOS. Table 2-5. Jumper Settings Jumper # Installed Removed JP1 – TFT/LCD Clock Clock Invert (pins 1-2) Clock Normal (pins 2-3) Default JP2 – LCD Voltage Type Enable +3.
Chapter 2 Product Overview Serial B (COM3/COM4) RS485 Termination (JP6) TFT/LCD Clock (JP1) J1 J3 4 3 U2 U12 U1 J2 Q11 J4 1 JP6 2 JP1 U32 Reserved Factory use only (J26) J5 U3 U4 J6 J26 D1 JP2 Y1 J7 U5 J8 U6 LCD Voltage Setting (JP2) U33 RB700_01cb J13 J9 J12 U7 U8 J10 J14 Y2 J11 U9 J15 Y3 CMOS Normal/ Clear (JP3) U10 D2 U11 J16 X1 Reset Switch (SW1) J19 J18 SW1 U15 X2 U14 D4 J21 J20 U13 U12 JP3 JP5 J22 BT1 J17 Power On/ IDE Activity LEDs (D4) JP4 CF Maste
Chapter 2 Product Overview Specifications Physical Specifications Table 2-9 lists the physical dimensions of the board. Figures 2-7 and 2-8 give the mounting dimensions, including side views, and Figure 2-7 shows the pin-1 connector locations. Table 2-9. Weight and Footprint Dimensions Item Dimension Weight 0.272kg. (0.60lb) Height (PC/104-Plus) 15.64mm (0.616”) Height (Overall) 28.75mm (1.132”) Width 115mm (4.5”) Length 165mm (6.5”) Thickness 1.574mm (0.
Chapter 2 Product Overview Thermal/Cooling Requirements The CPU, Northbridge, Southbridge, Secondary I/O, and voltage regulators are the sources of heat on the board. The ReadyBoard 700 is designed to operate at its maximum CPU speed of 400MHz, 650MHz, or 933MHz. All the processors and the Northbridge require a heatsink, but no fan. Mechanical Specifications 4.300 0.0 4.100 Figures 2-7 and 2-8 show the top view and side views of the ReadyBoard 700 with the mechanical mounting dimensions. 6.300 6.
Chapter 2 Product Overview ReadyBoard 700 (Side view) USB 0 & 1 Keyboard/ Power/IDE Ethernet 1 (J15A/B) Mouse Activity (J10) (USB 0 Lower) (J16A/B) LED (D4) Ethernet 2 Reset (J11) Switch CRT (J8) (SW1) RB700sideview01 Serial 1 & 2 (J5A/B) (Serial 1 Lower) CompactFlash Socket (J23) 6.500 0.100 0.624 0.068 0.602 0.055 0.072 0.696 0.510 0.640 0.120 1.113 0.497 0.361 0.650 0.547 0.370 0.390 0.051 0.624 0.080 0.345 1.214 0.067 0.275 1.213 0.180 0.554 0.275 0.500 0.311 Mounting 1.350 1.
Chapter 3 Hardware Overview This chapter discusses the chips and features of the connectors in the following order: • CPU (U4) • Memory (DIMM1) • PC/104-Plus (J12A, B, C, D) • PC/104 (J13A & B, J14C & D) • IDE Interfaces (J22) • CompactFlash Adapter (J23) • Floppy /Parallel Interface (J20) • Serial Interfaces (J5A/B, J3A/B) • USB (J15A/B, J21A/B) • Ethernet Interfaces (J10, J11) • Audio Interface (J19) • Video Interfaces (J8, J9, J7) • Miscellaneous ♦ Utility Interfaces (J18) ♦ Reset Switch (SW1)
Chapter 3 Hardware CPU (U4) The ReadyBoard 700 offers three Intel processor choices; high performance 933MHz Low Voltage (LV) Pentium® III processor, 650MHz Low Voltage (LV) Celeron® processor, or the low cost, 400MHz Ultra Low Voltage (ULV) Celeron processor. Celeron Processors The Celeron processors (Tualatin core) at 650MHz or 400MHz have 256kB L2 Cache on board and use a 100MHz FSB (front side bus). The Celeron processors require a heatsink, but no fan.
Chapter 3 Hardware Interrupt Channel Assignments The channel interrupt assignments are listed in Table 3-1. Table 3-1. Interrupt Channel Assignments Device vs IRQ No.
Chapter 3 Hardware Table 3-2.
Chapter 3 Hardware PC/104-Plus Interface (J12) The PC/104-Plus uses a 120-pin (30x4) 2mm header interface. This interface header carries all of the appropriate PCI signals operating at clock speeds up to 33MHz. The Northbridge, VT8606, integrates a PCI arbiter that supports up to four devices with three external PCI masters. This interface header accepts stackable modules and is located on the top of the board. Table 3-4 provides the signals and descriptions for each of the PCI bus pin-outs. Table 3-4.
Chapter 3 Pin # Signal 20 (A20) GND 21 (A21) AD29 22 (A22) +5V 23 (A23) REQ0* 24 (A24) GND Input/ Description Output Digital Ground T/S PCI Address and Data Bus Line 29 – Refer to Pin-3 for more information. +5 volt power supply ±5% T/S Bus Request 0 – This signal line is one of three signal lines. These signals indicate the device desires use of the bus to the arbitrator.
Chapter 3 Hardware Pin # Signal 47 (B17) AD23 48 (B18) GND 49 (B19) C/BE3* T/S PCI Bus Command/Byte Enable 3 – Refer to Pin-4 for more information. 50 (B20) AD26 T/S PCI Address and Data Bus Line 26 – Refer to Pin-3 for more information. 51 (B21) +5V 52 (B22) AD30 53 (B23) GND 54 (B24) REQ2* 55 (B25) VI/O 56 (B26) CLK0 57 (B27) +5V Input/ Description Output T/S PCI Address and Data Bus Line 23 – Refer to Pin-3 for more information.
Chapter 3 Hardware Pin # Signal 76 (C16) GND 77 (C17) AD22 78 (C18) IDSEL1 79 (C19) VI/O NC (+5V) Not connected 80 (C20) AD25 T/S PCI Address and Data Bus Line 25 – Refer to Pin-3 for more information. 81 (C21) AD28 T/S PCI Address and Data Bus Line 28 – Refer to Pin-3 for more information.
Chapter 3 Hardware Pin # Signal 106 (D16) AD19 Input/ Description Output T/S PCI Address and Data Bus Line 19 – Refer to Pin-3 for more information. 107 (D17) +3.3V +3.3 volt power supply ±5% 108 (D18) IDSEL2 Initialization Device Select 2 – Refer to Pin-18 for more information. 109 (D19) IDSEL3 Initialization Device Select 3 – Refer to Pin-18 for more information. 110 (D20) GND Digital Ground 111 (D21) AD27 T/S PCI Address and Data Bus Line 27 – Refer to Pin-3 for more information.
Chapter 3 Hardware PC/104 Interface (J13 A/B, J14 C/D) The PC/104 Bus uses a 104-pin 0.10” header interface. This interface header will carry all of the appropriate PC/104 signals operating at clock speeds up to 8MHz. This interface header accepts stackable modules and is located on the top of the board. Table 3-5.
Chapter 3 Hardware Pin # Signal Description (J13 Row A) 25 (A25) SA6 System Address 6 – Refer to SA19, pin-A12, for more information. 26 (A26) SA5 System Address 5 – Refer to SA19, pin-A12, for more information. 27 (A27) SA4 System Address 4 – Refer to SA19, pin-A12, for more information. 28 (A28) SA3 System Address 3 – Refer to SA19, pin-A12, for more information. 29 (A29) SA2 System Address 2 – Refer to SA19, pin-A12, for more information.
Chapter 3 Hardware Pin # Signal Descriptions (J13 Row B) 48 (B16) DRQ3 DMA Request 3 – Used by I/O resources to request DMA service. Must be held high until associated DACK3 line is active. 49 (B17) DACK1* DMA Acknowledge 1 – Used by DMA controller to select the I/O resource requesting the bus, or to request ownership of the bus as a bus master device. Can also be used by the ISA bus master to gain control of the bus from the DMA controller.
Chapter 3 Hardware Pin # Signal Descriptions (J14 Row C) 5 (C4) LA21 Lactchable Address 21 – Refer to LA23, pin-C2, for more information. 6 (C5) LA20 Lactchable Address 20 – Refer to LA23, pin-C2, for more information. 7 (C6) LA19 Lactchable Address 19 – Refer to LA23, pin-C2, for more information. 8 (C7) LA18 Lactchable Address 18 – Refer to LA23, pin-C2, for more information. 9 (C8) LA17 Lactchable Address 17 – Refer to LA23, pin-C2, for more information.
Chapter 3 Hardware 30 (D9) DRQ0 DMA Request 0 – Used by I/O resources to request DMA service. Must be held high until associated DACK0 line is active. 31 (D10) DACK5* DMA Acknowledge 5 – Used by DMA controller to select the I/O resource requesting the bus, or to request ownership of the bus as a bus master device. Can also be used by the ISA bus master to gain control of the bus from the DMA controller. 32 (D11) DRQ5 DMA Request 5 – Used by I/O resources to request DMA service.
Chapter 3 Hardware IDE Interface (J22) The ReadyBoard 700 provides one IDE connector (J22) for two IDE devices on the primary IDE controller and one CompactFlash socket (J23) on the secondary IDE controller. The EIDE interface logic supports the following features: • Transfer rate up to 100Mbps • Increased reliability using Ultra DMA 33/66/100 transfer protocols • Full scatter-gather capability • Supports ATAPI and DVD compliant devices • PIO IDE transfers as fast as 14Mbps.
Chapter 3 Hardware Pin # Signal Description 22 GND Digital Ground 23 PDIOW* Primary Device I/O Read/Write Strobe – Strobe signal for write functions. Negative edge enables data from a register or data port of the drive onto the host data bus. Positive edge latches data at the host. 24 GND Digital Ground 25 PDIOR* Primary I/O Read/Write Strobe – Strobe signal for read functions. Negative edge enables data from a register or data port of the drive onto the host data bus.
Chapter 3 Hardware CompactFlash Adapter (J23) The board contains a Type I or II PC card socket, which allows for the insertion of a CompactFlash Card. The CompactFlash Card acts as a standard IDE Drive and is connected to the Secondary IDE bus. If a CompactFlash card is installed, it is the only device using the secondary IDE bus. A Jumper is used to select the Master/Slave mode. Refer to Table 2-5, Jumper Settings for more information.
Chapter 3 Hardware Pin # Signal Description 25 CFD2 Connected through 4.7k ohm resister to ground 26 CFD1 Connected through 4.7k ohm resister to ground 27 SDD11 Secondary Disk Data 11 – Refer to SDD3 on pin-2 for more information. 28 SDD12 Secondary Disk Data 12 – Refer to SDD3 on pin-2 for more information. 29 SDD13 Secondary Disk Data 13 – Refer to SDD3 on pin-2 for more information. 30 SDD14 Secondary Disk Data 14 – Refer to SDD3 on pin-2 for more information.
Chapter 3 Hardware Floppy/Parallel Interface (J20) The Southbridge (VT82C686B) chip provides the floppy controller and the parallel port controller. The floppy controller and the parallel port controller share the same output connector (J20) on the board and the device selection is made in the BIOS Setup Utility. Refer to Table 4-2 for floppy configurations. • Floppy Port Controller supports two floppy drives (34-pin & USB), in the standard formats, such as 360k, 720k, 1.2M, 1.44M, or 2.88M drives.
Chapter 3 Hardware Pin # Signal Description 13 SLCTIN Select In – This output signal to the printer is used to select the printer. I/O pin in ECP/EPP mode. STEP* Step – Low pulse for each track-to-track movement of the head. 14 AUTOFDX* Auto Feed* – This is a request signal into the printer to automatically feed one line after each line is printed. DRVENO Floppy Drive Density Select 0 – 15 ERR* Error – This is a status output signal from the printer.
Chapter 3 Hardware Serial Interfaces (J5A/B, J3A/B) The ReadyBoard supports 4 independent serial ports, using two separate chips. The Southbridge (VT86C686B) provides serial ports 1 and 2 through the Serial A DB9 connector (J5A/B) and the Secondary I/O chip (W83877TF) provides serial ports 3 and 4 through Serial B connector (J3A/B).
Chapter 3 Hardware Serial A Interface (J5A/B) Table 3-12. Serial A (Serial 1) Interface Pin/Signal Descriptions (J5A) Pin # Signal Description 1 DCD1* Data Carrier Detect 1 – Indicates external serial communications device is detecting a carrier signal (i.e., a communication channel is currently open). In direct connect environments, this input will be driven by DTR1 as part of the DTR/DSR handshake.
Chapter 3 Hardware Serial B Interface (J3A/B) Table 3-14. Serial B Interface Pin/Signal Descriptions (J3A/B) Pin # Pin # DB9 Signal A1 (COM3) DCD3* Data Carrier Detect 3 – Indicates external serial communications device is detecting a carrier signal (i.e., a communication channel is currently open). In direct connect environments, this input will be driven by DTR3 as part of the DTR/DSR handshake.
Chapter 3 Hardware Pin # Pin # DB9 Signal Description B16 CTS4* Clear To Send 4 – Indicates external serial communications device is ready to receive data. Used as hardware handshake with RTS4 for low level flow control. RX4+ RX4+ – If in RS485 or RS422 mode, this pin is Receive Data 4 +. 8 B17 4 DTR4* Data Terminal Ready 4 – Indicator Serial port 4 is powered, initialized, and ready. Used as hardware handshake with DSR4 for overall readiness to communicate.
Chapter 3 Hardware USB Interfaces (J15A/B, J21A/B) The ReadyBoard 700 contains one root USB hub with four functional USB ports. The PC-style (or Standard) connector (J5A/B) provides two of the four USB ports (USB0 and USB1). The other two USB ports share a single 10 pin header (J21A/B) on the board. Features implemented in the USB ports include the following: • One root hub and two USB ports on connector (J15A/B) • One root hub and two USB ports on connector (J21A/B) • USB v.1.1 and Universal OHCI v.1.
Chapter 3 Hardware Ethernet Interfaces (J10, J11) The Ethernet solution is provided by two Intel 82551ER PCI controller chips, which consists of both the Media Access Controller (MAC) and the physical layer (PHY) combined into a single component solution. The 82551ER is a 32-bit PCI controller that features enhanced scatter-gather bus mastering capabilities, which enables the 82551ER to perform high-speed data transfers over the PCI bus.
Chapter 3 Hardware Table 3-18. Ethernet Port 2 Pin/Signal Descriptions (J11) Pin # GND Digital Ground 1 TX2+ 3 TX2- Analog Twisted Pair Ethernet Transmit Differential Pair. These pins transmit the serial bit stream for transmission on the Unshielded Twisted Pair Cable (UTP). These signals interface directly with an isolation transformer. 4 RX2+ 6 RX2- Analog Twisted Pair Ethernet Receive Differential Pair. These pins receive the serial bit stream from the isolation transformer.
Chapter 3 Hardware Video Interfaces (J8, J9, J7) The VT8606 chip provides the graphics control and video signals to the traditional glass CRT monitors and the LCD and LVDS flat panel displays. The chip features are listed below: CRT features: • Supports a max resolution of 1600 x 1200 with video frame buffer set at 8MB • Supports a maximum allowable video frame buffer size of 32MB UMA (Unified Memory Architecture) • AGP 4x graphics (always enabled) • Compliant with Rev 2.
Chapter 3 Hardware LCD Interface (J9) Table 3-21. LCD Interface Pin/Signal Descriptions (J9) Pin # Signal Description 1 NC Not connected 2 FP33 Flat Panel Data Output 33 – The mapping for these signals (0-35) changes with the type of flat panel selected in BIOS Setup. Refer to the notes for this table. 3 FP34 Flat Panel Data Output 34 – Refer to pin-2 for more information. 4 FP31 Flat Panel Data Output 31 – Refer to pin-2 for more information.
Chapter 3 Hardware Pin # Signal Description 39 FPDEN Flat Panel Data Enable – This signal to settle the horizontal display position. 40 FP0 Flat Panel Data Output 0 – Refer to pin-2 for more information. 41 FPCLKS Flat Panel Shift clock – This signal can be inverted by jumper JP1.
Chapter 3 Hardware Miscellaneous Utility Interface (J18) ♦ Power-On – This control signal is provided externally by connecting ground to pin-1 on the Utility connector (J18). ♦ Reset Switch – This signal is provided externally through a switch by connecting ground to pin-3 on the Utility connector (J18). This signal line is shared with Reset Switch (SW1).
Chapter 3 Hardware Infrared (IrDA) Port (J17) The Infrared Data Association (IrDA) control provides a two-way communications header for an external IrDA device using infrared as the transmission medium. There are two basic infrared implementations provided; the Hewlett-Packard Serial Infrared (HPSIR) and the Amplitude Shift Keyed Infrared (ASKIR) methods. HPSIR is a serial implementation of infrared developed by HewlettPackard.
Hardware 1 2 3 4 5 Serial 1 (J5A) Lower Port (COM1) Standard DB9 Serial Port Connector (Female) Rear View 6 7 8 9 RB700_Oops!jump Chapter 3 Figure 3-2. Oops! Jumper Connection User GPIO Signals (J2) The ReadyBoard 700 provides eight GPIO pins for custom use and the signals are routed to connector J2.
Chapter 3 Hardware Serial Console Setup The serial console feature is implemented by connecting a standard null modem cable or a modified serial cable (or “Hot Cable”) between one of the serial ports, such as Serial 1 (J5A), and the serial terminal or a PC with communications software. The BIOS Setup Utility controls the serial console settings on the ReadyBoard 700.
Chapter 3 Hardware Power Interfaces (J4, J6) The ReadyBoard 700 uses various voltages onboard, but only one voltage is required externally (+5 volts) through the external connector, which uses a 4-pin header with 0.200” spacing. The optional +12V volts is also provided on the input connector, but is not used on the board except for LCD panel power and for PCI or ISA bus power. All other onboard voltages are derived from the externally supplied +5 volts DC +/- 5%.
Chapter 3 54 Hardware Reference Manual ReadyBoard 700
Chapter 4 BIOS Setup Introduction This chapter describes the BIOS Setup menus and the various screens used for configuring the ReadyBoard 700. Some features in the Operating System or application software may require configuration in the BIOS Setup screens. This section assumes the user is familiar with general BIOS Setup and does not attempt to describe the BIOS functions. Refer to the appropriate PC reference manuals for information about the onboard ROM-BIOS software interface.
Chapter 4 BIOS Setup Accessing BIOS Setup (Serial Console) Entering the BIOS Setup, in serial console mode, is very similar to the steps you use to enter BIOS Setup with a VGA display, except the actual keys you use. 1. Set the serial terminal, or the PC with communications software to the following settings: ♦ 115k baud ♦ 8 bits ♦ One stop bit ♦ No parity ♦ No hardware handshake 2.
Chapter 4 BIOS Setup BIOS Menus BIOS Setup Opening Screen Ampro Setup Utility for ReadyBoard 700, SWxxxxxx Help for BIOS and Hardware Settings > BIOS and Hardware Settings < Reload Initial Settings Load Factory Default Settings Exit, Saving Changes Exit, Discarding Changes Use Arrow keys to change menu item, use Enter to select menu item (C) Copyright 2004, Ampro Computers, Inc. - http://www.ampro.com Figure 4-1.
Chapter 4 BIOS Setup BIOS Configuration Screen Ampro Setup Utility for ReadyBoard 700, SWxxxxxx [Date & Time] > Date Time [Drive Assignment] Drive A Drive B Drive C Drive D Drive E Drive F Drive G [Boot Order] Boot 1st Boot 2nd Boot 3rd Boot 4th Boot 5th Help for Date 08 Oct 2004< 10:24:34 1.44 MB, 3.5” (none) HDD on Pri Master (none) (none) (none) (none) The Date & Time fields are updated in real-time. When you make a change, the CMOS is updated immediately.
Chapter 4 BIOS Setup Table 4-2. Floppy Drive BIOS Settings # of Floppy Drive(s) BIOS Settings None • Set Drives A and B to [None] (1) Non-USB Floppy* • Configure Drive A to floppy drive type (For example, [1.44MB, 3.
Chapter 4 BIOS Setup rd ♦ Boot 3 – [none], [Drive A], [Drive B], [Drive C], [Drive D], [CDROM], [Alarm], or [Reboot] ♦ Boot 4th – [none], [Drive A], [Drive B], [Drive C], [Drive D], [CDROM], [Alarm], or [Reboot] ♦ Boot 5th – [none], [Drive A], [Drive B], [Drive C], [Drive D], [CDROM], [Alarm], or [Reboot] ♦ Boot 6th – [none], [Drive A], [Drive B], [Drive C], [Drive D], [CDROM], [Alarm], or [Reboot] NOTE The default Boot order is, A, C, CD-ROM, and the BIOS will start its search for a bootable dev
Chapter 4 BIOS Setup • Keyboard and Mouse (Configuration) ♦ Numlock – [Disabled] or [Enabled] ♦ Typematic – [Disabled] or [Enabled] This field is used for the keyboard. ♦ Delay – [250ms], [500ms], [750ms], or [1000ms] This field is used for the keyboard and determines how many milliseconds the keyboard controller waits before stating to repeat a key, if the key is held down on the keyboard.
Chapter 4 BIOS Setup ♦ Memory Hole – [Disabled], [1MB], or [2MB] This field specifies the size of an optional memory hole, below 16MB. Access to the memory addresses inside the memory hole region are forwarded to the PC/104 bus, where memory mapped PC/104 devices have access. ♦ Shadow D000-D3FF – [Disabled] or [Enabled] These Shadow fields specify if BIOS option ROMs in the indicated segments should be shadowed to RAM. Shadowing option ROMs can potentially speed up the operation of the system.
Chapter 4 BIOS Setup ♦ Watchdog Timeout (sec) – [select whole number between 255 seconds and 1 second, in 1 second increments] or [Disabled] If this field is enabled by selecting a time interval (1 to 255 seconds), it will direct the watchdog timer to reset the system if it fails to boot the OS properly. Refer to the watchdog timer section in Chapter 3 for more information.
Chapter 4 BIOS Setup • On-Board Serial Ports NOTE ♦ Serial Ports 1 and 2 can not share the same IRQs, and the IRQs used for Serial Ports 1 and 2 can not be used for Serial Ports 3 and 4 and vice versa. Serial 1 – [Disabled], [3F8h], [2F8h], [3E8h], [2E8h], [260h], [2F0h], [3E0h], [2E0h], [200h], or [220h] This field specifies the base address used for Serial Port 1. • IRQ – [none], [1], [3], [4], [5], [6], [7], [9], [10], [11], [12], [14], or [15] This field specifies the IRQ used for Serial Port 1.
Chapter 4 BIOS Setup • DMA – [3], [2], [1], or [0] This field specifies the DMA channel used for the Parallel Port (LPT 1). If the LPT 1 field is set to [Disabled], then no DMA channel is assigned, making it available for other devices. • Mode – [Standard], [SPP (bi-dir)], [EPP 1.9 + SPP], [EPP 1.7 + ECP], [EPP 1.9 + ECP], or [ECP] This field specifies the Mode used for Parallel Port (LPT 1).
Chapter 4 BIOS Setup ♦ Panel Type – [640 x 480 x 18 TFT] Refer to Table 4-3 for the list of supported resolutions and flat panel types. Some LCD panels may require video BIOS modifications. It you think this is the case, or would like help in setting up your LCD panel, contact Ampro for assistance with the LCD panel adaptation. Table 4-3.
Chapter 4 BIOS Setup ♦ PnP OS – [Disabled] or [Enabled] If this field is set to [Enabled], the BIOS makes the Plug and Play API available for Plug and Play Operating Systems. This allows the Plug and Play OS to get the Plug and Play information by calling the Plug and Play API. ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ Assign IRQ 1 – [Disabled] or [Enabled] • If this field is set to [Enabled], then the BIOS can assign this IRQ to a Plug and Play adapter.
Chapter 4 BIOS Setup ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ 68 Assign IRQ 11 – [Disabled] or [Enabled] (Typically ISA Bridge/Native IDE) • If this field is set to [Enabled], then the BIOS can assign this IRQ to a Plug and Play adapter. • If another device in the system is using this IRQ, then this field should be set to [Disabled]. Assign IRQ 12 – [Disabled] or [Enabled] (Typically PS/2 Mouse) • If this field is set to [Enabled], then the BIOS can assign this IRQ to a Plug and Play adapter.
Chapter 4 BIOS Setup ♦ ♦ ♦ Assign DMA 5 – [Disabled] or [Enabled] • If this field is set to [Enabled], then the BIOS can assign this DMA channel to a Plug and Play adapter. • If another device in the system is using this DMA channel, then this field should be set to [Disabled]. Assign DMA 6 – [Disabled] or [Enabled] • If this field is set to [Enabled], then the BIOS can assign this DMA channel to a Plug and Play adapter.
Chapter 4 BIOS Setup Splash Screen Customization The ReadyBoard 700 BIOS supports a graphical splash screen, which can be customized by the user and displayed on screen when enabled through the BIOS Setup Utility. The graphical image can be a company logo or any custom image the user wants to display during the boot process. The custom image can be displayed as the first image displayed on screen during the boot process and remain there, depending on the options selected in BIOS Setup, while the OS boots.
Chapter 4 BIOS Setup Use the following steps to convert and load your custom image onto the ReadyBoard 700. 1. Copy the files from the RB700\software\examples\splash directory on the CD-ROM to a new directory (conversion directory) on your PC. This new conversion directory is where you intend to do the conversion and save the file. 2. Ensure you remove the read-only attributes from all the files as part of the file copying process. 3. Copy the ReadyBoard 700 BIOS binary file (rb700.
Chapter 4 72 BIOS Setup Reference Manual ReadyBoard 700
Appendix A Technical Support Ampro Computers, Inc. provides a number of methods for contacting Technical Support listed in the Table A-1 below. Requests for support through the Virtual Technician are given the highest priority, and usually will be addressed within one working day. • Ampro Virtual Technician – This is a comprehensive support center designed to meet all your technical needs. This service is free and available 24 hours a day through the Ampro web site at http://ampro.custhelp.com.
Appendix A 74 Technical Support Reference Manual ReadyBoard 700
Appendix B LAN Boot Option The LAN Boot feature is optional for the ReadyBoard 700 and you must contact Ampro or your sales representative for more information before you can make use of this option. The LAN Boot option requires a BIOS update, installed by Ampro, to make use of the LAN Boot features. Introduction LAN Boot is supported by both Ethernet ports on the ReadyBoard 700, and is based on the Preboot Execution Environment (PXE), an open industry standard.
Appendix B LAN Boot Option PXE Boot Agent BIOS Setup This section describes the BIOS settings of the third party PXE Boot agent provided by Ampro and integrated into the ReadyBoard 700 firmware upgrade. The PXE Boot Agent’s BIOS setup menu and screens are used when configuring the LAN boot feature in the ReadyBoard 700 BIOS. The third party PXE Boot agent provided by Ampro supports multiple boot protocols and network environments such as traditional TCP/IP, NetWare, and RPL.
Appendix B LAN Boot Option PXE Boot Agent Setup Screen Argon Managed PC Boot Agent (MBA) v4.
Appendix B LAN Boot Option • NetWare Configuration ♦ Boot Method: – [PXE], [TCP/IP], [NetWare], or [RPL] ♦ Protocol: – [802.2], [802.
Index 400MHz CPU heatsinks required ............................................17 650MHz CPU heatsinks required ............................................17 933MHz CPU heatsinks required ............................................17 Ampro Products CoreModule Family .......................................2 EnCore Family ...............................................3 ETX Family .......................................................3 Little Board Family ........................................
Index Power On .........................................................14 Lithium Battery external connection ..........................................50 RTC..................................................................50 major integrated circuit (chip) specifications web sites.............................................................2 memory map ........................................................21 no bootable device available ................................
Appendix B LAN Boot Option Celeron CPUs ..............................................6, 20 CompactFlash socket (1)..............................7, 35 console redirection ...........................................51 Ethernet interfaces (2)..................................8, 44 Ethernet port LEDs ..........................................14 external battery...................................................8 flat panel configurations ..................................66 floppy disk drives (2) ...........
Index 82 Reference Manual ReadyBoard 700
