LittleBoard™ 550 Single Board Computer Reference Manual P/N 5001740A Revision A
Notice Page NOTICE No part of this document may be reproduced, transmitted, transcribed, stored in a retrieval system, or translated into any language or computer language, in any form or by any means, electronic, mechanical, magnetic, optical, chemical, manual, or otherwise, without the prior written permission of Ampro Computers, Incorporated.
Contents Chapter 1 About This Manual .........................................................................................................1 Purpose of this Manual.......................................................................................................................1 Reference Material .............................................................................................................................1 Related Ampro Products ........................................................
Contents USB Signals (USB0 and USB1) .................................................................................................. 49 Utility 3 Interface (J18) ..................................................................................................................... 51 USB Signals (USB2 and USB3) .................................................................................................. 51 Ethernet Interfaces (J7, J32)..................................................................
Contents Figure 2-4. Figure 2-5. Figure 2-6. Figure 2-7. Figure 2-8. Figure 3-1. Figure 3-2. Figure 3-3. Figure 4-1. Figure 4-2. Figure B-1. Connector and Fuse Locations (Top view) ...................................................................13 Jumpers Locations (Top view) ......................................................................................15 Component and Fuses Locations (Bottom view) ..........................................................
Contents Table 3-28. CPU Fan (J2) ............................................................................................................... 61 Table 4-1. BIOS Setup Menus ........................................................................................................ 64 Table 4-2. Floppy Drive BIOS Settings ........................................................................................... 67 Table 4-3. LCD Panel Type List...............................................................
Chapter 1 About This Manual Purpose of this Manual This manual is for designers of systems based on the LittleBoard™ 550 single board computer (SBC). This manual contains information that permits designers to create an embedded system based on specific design requirements.
Chapter 1 About this Manual Chip (integrated circuits) specifications used on the LittleBoard 550: • VIA Technologies, Inc. the Eden™ ESP processors, and the chips, VT8606 and VT82C686B, used for the Northbridge/Video controller and Southbridge respectively Web site: http://www.viatech.com • Winbond Electronics, Corp. and the W83877TF chip used for the secondary I/O controller Web site: http://www.winbond-usa.com/products/winbond_products/pdfs/PCIC/877tf.
Chapter 1 About this Manual • LittleBoard 800 – This EBX single board computer (SBC) is a highly integrated, highperformance, rugged, high quality system based on Intel's 1.4GHz Low Voltage Pentium M 738, 1.0GHz Low Voltage Celeron M, or 600MHz Ultra Low Voltage Celeron M CPUs. In addition to the standard LittleBoard features (EBX form factor, PC/104 & PC/104-Plus interfaces, +5 volt power, watchdog timer, serial console, etc.
Chapter 1 About this Manual • EnCore™ Family – These high-performance, compact, rugged Computer-on-Module (COM) solutions use various processor technologies including x86, MIPS®, and PowerPC™ architectures to plug into your custom baseboard. Each EnCore module provides standard peripherals, including Ultra/DMA 33/66/100 IDE, floppy drive interface, PCI bus, serial, parallel, PS/2 keyboard and mouse interfaces, 10/100BaseT Ethernet, and USB ports. Some EnCore modules also provide video and AC’97 sound.
Chapter 2 Product Overview This introduction presents general information about the EBX Architecture and the LittleBoard 550 single board computer (SBC).
Chapter 2 Product Overview 4-40 screws (4) PC/104 Module 0.6 inch spacers (4) PC/104 Plus Module PCI Stackthrough Headers LittleBoard 550 0.6 inch spacers (4) 4-40 nuts (4) LB550stackthru Stackthrough Expansion Bus Headers Figure 2-1.
Chapter 2 Product Overview Board Features • CPU features ♦ Via Eden™ ESP 10000 (1GHz), Eden ESP 5000 (533MHz) or Eden ESP 3000 (300MHz) ♦ Each CPU has a Front Side Bus (FSB) of 133MHz, 133MHz, or 66MHz, respectively • Memory ♦ Provides a single standard 168-pin DIMM slot ♦ Supports +3.3V SDRAM up to 1GB ♦ Supports 133MHz (7.
Chapter 2 Product Overview ♦ Supports RS232, RS485, or RS422 operation on each port ♦ Supports programmable word length, stop bits, and parity ♦ Supports 16-bit programmable baud-rate generator and a interrupt generator. • Parallel Port ♦ Supports standard printer port ♦ Supports IEEE standard 1284 protocols of EPP and ECP outputs ♦ Bi-directional data lines ♦ Supports 16 byte FIFO for ECP mode.
Chapter 2 Product Overview • Video Interfaces (CRT/LVDS) ♦ Supports CRT (1600 x 1200) with 32MB SMA (Shared Memory Area) ♦ AGP 4X graphics ♦ Compliant with Rev 2.
Chapter 2 Product Overview Block Diagram Figure 2-3 shows the functional components of the board. VIA EDEN™ CPU Clock CRT VGA Northbridge VT8606 Memory Bus LVDS LCD PC104-Plus Bus Connector Ethernet Controller 82251ER SDRAM SODIMM SMBus PCI Bus ATA Southbridge VT82C686B IrDA 1.1 IDE Primary IDE Secondary IDE Devices, (HDDs, CompactFlash, CD-ROM, etc.
Chapter 2 Product Overview Major Integrated Circuits (ICs) Table 2-1 lists the major integrated circuits, including a brief description of each, on the LittleBoard 550 and Figure 2-4 shows the location of the major chips. Table 2-1. Major Integrated Circuit Description and Function Chip Type CPU (U1) Mfg. Model VIA Eden ESP 10000, Technologies, Inc. ESP 5000, ESP 3000 Description CPUs offered at 1GHz, 533MHz, and 300MHz Function Embedded CPU Northbridge (U2) VIA VT8606 (Twister-T) Technologies, Inc.
Chapter 2 Product Overview Connector Definitions Table 2-2 describes the connectors shown in Figures 2-3 to 2-5. All I/O connectors use 0.1” pin spacing unless otherwise indicated. Table 2-2. Connector Descriptions Jack # Signal Description J1A/J1B & PC/104 bus J1C, J1D 104-pins for PC/104 connector J2 Fan connector 3-pin header provides +5v and ground to fan.
Chapter 2 Product Overview CRT (J5) L9 LCD 2 (J4) LCD 1 (J3) CRT Fuse (F5) J5 J3 L8 F5 J4 Fan (J2) DIMM1 J2 CPU (U1) DIMM1 L2 ge id br th 2) or U N ( L3 LVDS (J31) J18 U34 L5 J31 U10 E th (U e rn 5) e t U21 U27 J21 ge r id hb ) ut U3 So ( U15 J1 Audio In/ Out (J28) U26 E th e (U rn e 6) t U25 J28 Y5 PC/104-Plus (J21) U22 Y1 U4 U24 LB550A_01b Utility 3 (J18) U33 U23 U11 J23 U16 U20 U17 U19 JP5 JP6 BAT1 CompactFlash Socket (J23) Ethernet Port 2 (J32) U9 JP4
Chapter 2 Product Overview Jumper Definitions Table 2-4 describes the jumpers shown in Figure 2-5. Table 2-4. Jumper Settings Jumper # Installed Removed/Installed JP3 – CompactFlash Voltage Select Enable +5V (1-2) (Default) Enable +3.
Product Overview L9 J5 J3 L8 F5 J4 LB550_01c Chapter 2 J2 CPU (U1) DIMM1 L2 ge rid hb ) rt U2 No ( L3 J18 U34 L5 J31 et rn he 5) Et (U U10 U21 U27 J21 et rn ) he 6 Et (U ge rid hb ) ut U3 So ( U15 J1 U26 U25 U22 Y1 U4 U24 COM1 RS485 Term (JP5) J28 Y5 J23 U16 U23 U11 COM2 RS485 Term (JP6) U33 U20 U17 JP6 BAT1 U19 JP5 U9 JP4 CF Master/ Slave (JP4) JP3 JP8 J11 J13 J15 U14 CF Voltage Select (JP3) JP7 U12 U8 J7 J32 U7 COM3 RS485 Term (JP7) J14 J17 J24 J
Product Overview LB550_02a D6 D4 Q13 Q14 U39 Chapter 2 D7 D8 Q4 U28 Q2 Q1 U30 Q3 Y3 USB1 Fuse (F2) Y4 F2 USB0 Fuse (F1) F1 F4 USB3 Fuse (F4) Y2 F3 USB2 Fuse (F3) U13 Super I/O Controller (U13) Figure 2-6. Component and Fuses Locations (Bottom view) Specifications Physical Specifications Table 2-7 gives the physical dimensions of the board and Figures 2-7 and 2-8 give the mounting dimensions and pin-1 connector locations. Table 2-7.
Chapter 2 Product Overview Mechanical Specifications 5.350 4.050 3.965 1.650 0.580 0.0 0.230 Figures 2-7 and 2-8 show top views of the LittleBoard 550 with the mechanical mounting dimensions. 7.800 7.600 7.500 7.450 7.150 7.115 7.050 7.600 5.800 5.700 3.915 3.500 3.100 2.800 2.700 2.650 2.458 LB550_01d 2.200 0.245 0.0 -0.075 -0.200 5.350 5.550 4.950 5.250 4.025 3.160 1.875 1.356 0.705 0.325 -0.200 0.0 0.0 Figure 2-7.
5.350 4.050 3.200 2.730 1.415 0.705 0.115 Product Overview 0.0 Chapter 2 7.800 7.600 7.600 7.050 6.800 LB550_01e 6.385 6.350 6.345 0.719 0.0 0.0 -0.200 -0.107 0.0 0.235 5.350 5.550 -0.200 Figure 2-8. LittleBoard 550 Dimensions (Top view, #2) NOTE 18 All dimensions are given in inches.
Chapter 2 Product Overview Power Specifications Table 2-8 shows the power requirements for the LittleBoard, including the I/O interface board. Table 2-8. Power Supply Requirements Parameter 300MHz Characteristics 533MHz Characteristics 1GHz Characteristics Input Type Regulated DC voltages Regulated DC voltages Regulated DC voltages In-rush* Current 26.9Amps (134.5W) (Typical) 20.6Amps (103W) 25.9Amps (129.5W) BIT** Current (Typical) 2.51Amps (12.55W) 2.84Amps (14.21W) 1.98Amps (9.
Chapter 2 20 Product Overview Reference Manual LittleBoard 550
Chapter 3 Hardware Overview This chapter discusses the chips and features of the connectors in the following order: • CPU (U1) • Memory • PC/104-Plus (J21A, B, C, D) • PC/104 (J1A, B, C, D) • IDE Interfaces (J12, J17) • CompactFlash Adapter (J23) • Floppy Interface (J14) • Serial Interfaces (J11, J13) • Parallel Interface (J15) • Utility Interfaces (J16, J18, J24) ♦ Keyboard ♦ Mouse ♦ Battery ♦ Reset Switch ♦ Speaker ♦ USB ♦ SMBus • Ethernet Interfaces (J7, J32) • Audio Interface (J28) • V
Chapter 3 Hardware CPU (U1) The LittleBoard 550 offers three VIA Technologies Eden processor choices; high performance 1GHz ESP 10000 processor, 533MHz ESP 5000 processor, or the low cost, 300MHz ESP3000 processor. ESP Processors The ESP (0.13µ or 0.15µ) processors at 1GHz, 533MHz, or 300MHz use 133MHz, 133MHz, or 66MHz FSB (front side bus) respectively, with 128kB Level 1 cache and 64kB Level 2 cache. The ESP processors require a heatsink, but no fan.
Chapter 3 Hardware Interrupt Channel Assignments The channel interrupt assignments are shown in Table 3-1. Table 3-1. Interrupt Channel Assignments Device vs IRQ No.
Chapter 3 Hardware Table 3-2.
Chapter 3 Hardware PC/104-Plus Interface (J21) The PC/104-Plus uses a 120-pin (30x4) header interface. This interface header carries all of the appropriate PCI signals operating at clock speeds up to 33MHz. The Northbridge, VT8606, integrates a PCI arbiter that supports up to four devices with three external PCI masters. This interface header accepts stackable modules and is located on the top of the board. Table 3-4 provides the signals and descriptions for the PC/104-Plus bus pin-outs.
Chapter 3 Hardware Pin # Signal 18 (A18) IDSEL0 19 (A19) AD24 20 (A20) GND 21 (A21) AD29 22 (A22) +5V 23 (A23) REQ0* 24 (A24) GND Ground T/S PCI Address and Data Bus Line 29 – Refer to Pin 3 for more information. +5 volts ±5% power supply T/S Bus Request 0 – This signal line is one of three signal lines. These signals indicate the device desires use of the bus to the arbitrator. Ground T/S Grant 1 – This signal line is one of three signal lines.
Chapter 3 Hardware Pin # Signal 45 (B15) +3.3V 46 (B16) AD20 47 (B17) AD23 48 (B18) GND Input/ Description Output +3.3 volts ±5% power supply T/S PCI Address and Data Bus Lines 20 – Refer to Pin 3 for more information. T/S PCI Address and Data Bus Line 23 – Refer to Pin 3 for more information. Ground 49 (B19) C/BE3* T/S 50 (B20) AD26 T/S 51 (B21) +5V 52 (B22) AD30 53 (B23) GND PCI Bus Command/Byte Enable 3 – Refer to Pin 4 for more information.
Chapter 3 Hardware Pin # Signal 74 (C14) +3.3V 75 (C15) AD17 76 (C16) GND 77 (C17) AD22 78 (C18) IDSEL1 79 (C19) VI/O NC (+5V) Not connected 80 (C20) AD25 T/S PCI Address and Data Bus Line 25 – Refer to Pin 3 for more information. 81 (C21) AD28 T/S PCI Address and Data Bus Line 28 – Refer to Pin 3 for more information.
Chapter 3 Hardware Pin # Signal 103 (D13) +3.3V Input/ Description Output +3.3 volts ±5% power supply 104 (D14) C/BE2* PCI Bus Command/Byte Enable 2 – Refer to Pin 4 for more information. 105 (D15) GND Ground 106 (D16) AD19 T/S PCI Address and Data Bus Line 19 – Refer to Pin 3 for more information. 107 (D17) +3.3V +3.3 volts ±5% power supply 108 (D18) IDSEL2 Initialization Device Select 2 – Refer to Pin 18 for more information.
Chapter 3 Hardware PC/104 Interface (J1A,B,C,D) The PC/104 Bus uses a 104-pin 100 mil header interface. This interface header will carry all of the appropriate PC/104 signals operating at clock speeds up to 8MHz. This interface header accepts stackable modules and is located on the top of the board. NOTE To conform to the PC/104 standard, keys have been inserted into specific pins in the PC/104 connector (B10, C19). Table 3-5.
Chapter 3 Hardware Pin # Signal Description (J1 Row A) 23 (A23) SA8 System Address 8 – Refer to SA19, pin-A12, for more information. 24 (A24) SA7 System Address 7 – Refer to SA19, pin-A12, for more information. 25 (A25) SA6 System Address 6 – Refer to SA19, pin-A12, for more information. 26 (A26) SA5 System Address 5 – Refer to SA19, pin-A12, for more information. 27 (A27) SA4 System Address 4 – Refer to SA19, pin-A12, for more information.
Chapter 3 Hardware Pin # Signal Descriptions (J1 Row B) 47 (B15) DACK3* DMA Acknowledge 3 – Used by DMA controller to select the I/O resource requesting the bus, or to request ownership of the bus as a bus master device. Can also be used by the ISA bus master to gain control of the bus from the DMA controller. 48 (B16) DRQ3 DMA Request 3 – Used by I/O resources to request DMA service. Must be held high until associated DACK3 line is active.
Chapter 3 Hardware Table 3-7. PC/104 Interface Pin/Signal Descriptions (J1C) Pin # Signal Descriptions (J1 Row C) 1 (C0) GND Ground 2 (C1) SBHE* System Byte High Enable – This signal is driven low to indicate a transfer of data on the high half of the data bus (D15 to D8). 3 (C2) LA23 Lactchable Address 23 – This signal must be latched by the resource if the line is required for the entire data cycle. 4 (C3) LA22 Lactchable Address 22 – Refer to LA23, pin-C2, for more information.
Chapter 3 Hardware Pin # Signal Descriptions (J1 Row D) 27 (D6) IRQ15 Interrupt Request 15 – Asserted by a device when it has pending interrupt request. Only one device may use the request line at a time. 28 (D7) IRQ14 Interrupt Request 14 – Asserted by a device when it has pending interrupt request. Only one device may use the request line at a time.
Chapter 3 Hardware IDE Interface (J12, J17) The LittleBoard 550 provides two IDE connectors for primary and secondary IDE signals. The EIDE interface logic supports the following features: • Transfer rate up to 100Mbps • Increase reliability using Ultra DMA 33/66/100 transfer protocols • Full scatter-gather capability • Supports ATAPI and DVD compliant devices • PIO IDE transfers as fast as 14Mbps. • Bus master IDE transfers as fast as 100Mbps.
Chapter 3 Hardware Pin # Signal Description 21 PDREQ Primary DMA Request – Used for DMA transfers between host and drive (direction of transfer controlled by PDIOR* and PDIOW*). Also used in an asynchronous mode with PDACK*. Drive asserts PDREQ when ready to transfer or receive data. 22 GND Ground 23 PDIOW* Primary I/O Write Strobe – Strobe signal for write functions. Negative edge enables data from a register or data port of the drive onto the host data bus.
Chapter 3 Hardware Pin # Signal Description All Task File operations occur in byte mode on the low order bus D0-D7, while all data transfers are 16 bit using D0-D15 to provide the disk data signals. 4 SDD8 Secondary Disk Data 8 – Refer to SDD7 on pin-2 for more information. 5 SDD6 Secondary Disk Data 6 – Refer to SDD7 on pin-2 for more information. 6 SDD9 Secondary Disk Data 9 – Refer to SDD7 on pin-2 for more information.
Chapter 3 Hardware Pin # Signal Description 33 SDA1 Secondary Disk Address 1 – One of three signals (0 – 2) used to indicate which byte in the ATA command block or control block is being accessed. 34 SD33_66 UDMA 33/66 Sense – Used to detect the presence of an 80 conductor IDE cable on the secondary IDE channel. Enables BIOS to sense which DMA mode to use for IDE devices. 35 SDA0 Secondary Disk Address 0 – Refer to SDA1 on pin-33 for more information.
Chapter 3 Hardware CompactFlash Adapter (J23) The board contains a Type II PC card socket, which allows for the insertion of a CompactFlash Card. The CompactFlash (CF) Card acts as a standard IDE Drive and is connected to the primary IDE bus. If a CompactFlash card is installed, only one additional IDE drive may be added to the primary bus. Jumpers are used to select the Master/Slave mode and the voltage selection (+5V or +3.3V). Refer to Table 2-4, Jumper Settings for more information. Table 3-11.
Chapter 3 Hardware Pin # Signal Description 31 PDD15 Disk Data 15 – Refer to PDD3 on pin-2 for more information. 32 PDCE2* Primary Slave/Master Chip Select – This signal, along with CE1*, selects the CompactFlash card and indicates to the card when a byte or word operation is being performed. This signal always accesses the odd byte of the word.
Chapter 3 Hardware Floppy Drive Interface (J14) The VT82C686B chip provides the floppy controller and supports two floppy drives. The floppy signals are provided through the standard 34-pin connector (J14). The floppy controller will support the 360k, 720k, 1.2M, 1.44M, and 2.88M drives. USB floppy disk drives are also supported. Table 3-12.
Chapter 3 Hardware Parallel Port Interface (J15) Parallel port supports standard parallel, Bi-directional, ECP and EPP protocols. The VIA Southbridge provides the parallel port interface signals. Table 3-13. Parallel Interface Pin/Signal Descriptions (J15) Pin # Signal In/Out Description 1 Strobe* Out Strobe* – This is an output signal used to strobe data into the printer. I/O pin in ECP/EPP mode.
Chapter 3 Hardware Serial Interfaces (J11, J13) Two chips provide the circuitry for the 4 serial ports. The VT86C686B provides serial ports 1 and 2 through connector J11 and the Super I/O provides serial ports 3 and 4 through connector J13.
Chapter 3 Hardware Table 3-14. Serial A Interface Pin/Signal Descriptions (J11) Pin # Pin # DB9 1 1 (COM1) Description DCD1* Data Carrier Detect 1 – Indicates external serial communications device is detecting a carrier signal (i.e., a communication channel is currently open). In direct connect environments, this input will be driven by DTR1 as part of the DTR/DSR handshake. 2 6 DSR1* Data Set Ready 1 – Indicates external serial communications device is powered, initialized, and ready.
Chapter 3 Hardware Pin # Pin # DB9 16 8 Signal Description CTS2* Clear To Send 2 – Indicates external serial communications device is ready to receive data. Used as hardware handshake with RTS2 for low level flow control. RX2+ RX2+ – If in RS485 or RS422 mode, this pin is Receive Data 2 -. 17 4 DTR2* Data Terminal Ready 2 – Indicates Serial port 2 is powered, initialized, and ready. Used as hardware handshake with DSR2 for overall readiness to communicate.
Chapter 3 Hardware Pin # Pin # DB9 11 1 (COM4) Signal Description DCD4* Data Carrier Detect 4 – Indicates external serial communications device is detecting a carrier signal (i.e., a communication channel is currently open). In direct connect environments, this input will be driven by DTR4 as part of the DTR/DSR handshake. 12 6 DSR4* Data Set Ready 4 – Indicates external serial communications device is powered, initialized, and ready.
Chapter 3 Hardware Utility Interfaces The Utility interfaces consists of three connectors that provide the standard interface signals, which include the: • Utility 1 ♦ Keyboard ♦ External battery connection ♦ Reset Switch ♦ PC Speaker • Utility 2 ♦ PS/2 Mouse ♦ SMBus signals ♦ USB signals for USB ports 1 and 2 ♦ Power button signal • Utility 3 ♦ USB signals for USB ports 3 (USB0) and 4 (and USB1) Utility 1 Interface (J16) Utility 1 interface consists of a 16-pin connector and is used t
Chapter 3 Hardware Table 3-16.
Chapter 3 Hardware Table 3-17. SMBus Reserved Addresses Component Address Binary Serial EEPROM (SEEP) 1010,010xb SDRAM EPROM 1010,000xb Clock Generator (ICS9250) 1101,001xb Southbridge (VT82C686B) 0000,000xb (default) Programmable Master Thermal Sensor (MAX1617) 0011,0010xb USB Signals (USB0 and USB1) The LittleBoard 550 contains one root USB hub with four functional USB ports. This connector (Utility 2) provides two of the four USB ports (USB0 and USB1). The hub is USB v.1.
Chapter 3 Hardware Table 3-18.
Chapter 3 Hardware Utility 3 Interface (J18) The Utility 3 interface is a 10-pin connector used to provide the two of the USB port signals to an external board with USB connections or directly to the respective USB connector for the USB ports. Table 3-19 gives the pin outs and interface signals for Utility 3 interface. • USB ports 2 (USB2) and 3 (USB3) USB Signals (USB2 and USB3) The LittleBoard 550 contains one root USB hub with four functional USB ports.
Chapter 3 Hardware Ethernet Interfaces (J7, J32) The Ethernet solution is provided by two Intel 82551ER PCI controller chips, which consists of both the Media Access Controller (MAC) and the physical layer (PHY) combined into a single component solution. The 82551ER is a 32-bit PCI controller that features enhanced scatter-gather bus mastering capabilities, which enables the 82551ER to perform high-speed data transfers over the PCI bus.
Chapter 3 Hardware Table 3-21. Ethernet Port 2 Pin/Signal Descriptions (J32) Pin # Signal Description 1 TX+ 2 TX- Analog Twisted Pair Ethernet Transmit Differential Pair. These pins transmit the serial bit stream for transmission on the Unshielded Twisted Pair Cable (UTP). These signals interface directly with an isolation transformer. 3 RX 6 RX- Analog Twisted Pair Ethernet Receive Differential Pair. These pins receive the serial bit stream from the isolation transformer.
Chapter 3 Hardware Table 3-22.
Chapter 3 Hardware Video Interfaces (J3, J4, J5, J31) The Northbridge (VT8606) chip provides the graphics control and video signals to the traditional glass CRT monitors and the LCD and LVDS flat panel displays. The chip features are listed below: CRT features: • Supports a max resolution of 1600 x 1200 with video frame buffer set at 8MB • Supports a maximum allowable video frame buffer size of 32MB shared memory • AGP 4X graphics (always enabled) • Compliant with Rev 2.
Chapter 3 Hardware LCD Interface 1 Table 3-24. LCD Interface 1 Pin/Signal Descriptions (J3) 56 Pin # Signal Description 1 GND Ground 2 +3.3V +3.
Chapter 3 Hardware Pin # Signal Description 39 ENAVDD Power sequencing output for LCD driver 40 GND Ground 41 FP20 Flat Panel Data Output 20 – Refer to pin 12 for more information. 42 FP21 Flat Panel Data Output 21 – Refer to pin 12 for more information. 43 FP22 Flat Panel Data Output 22 – Refer to pin 12 for more information. 44 +3.3V +3.3V +/- %5 45 FP23 Flat Panel Data Output 23 – Refer to pin 12 for more information.
Chapter 3 Hardware LVDS Interface Table 3-26. LVDS Interface Pin/Signal Descriptions (J31) Pin # Signal Description 1 3.3V_Panel +3.
Chapter 3 Hardware Miscellaneous Real Time Clock (RTC) The LittleBoard 550 contains a Real Time Clock (RTC) and along with the CMOS RAM are backed up with a Lithium Battery. If the battery is not present or has failed the BIOS has a battery-free boot option to complete the boot process. Temperature Monitoring The MAX1617 performs the temperature monitoring function and has an inputs from the thermal diode in the VIA Eden CPUs.
Chapter 3 Hardware 19 Serial A Interface (J11) for Serial Port 1 (or COM1 Port) Top View 97531 1 2 3 4 5 Or Standard DB9 Serial Port Connector (Female) 20 10 8 6 4 2 Rear View LB550Hotcable for the serial port 1. As an alternate, you can short the equivalent pins (pins 7 and 9) on the respective DB9 port connector as shown in Figure 3-3. 6 7 8 9 Figure 3-3.
Chapter 3 Hardware Power Interface (J10) The LittleBoard 550 uses five separate voltages on the board, but only one of the voltages is provided externally (+5 volts) through the external connector, which uses a 7-pin vertical header with 0.156” (3.96mm) spacing. Holes for a right angle mounting header are also available at J10. All the onboard voltages are derived from the externally supplied +5 volts DC +/- 5%.
Chapter 3 62 Hardware Reference Manual LittleBoard 550
Chapter 4 BIOS Setup Introduction This chapter describes the BIOS Setup menus and the various screens used for configuring the LittleBoard 550. Some features in the Operating System or application software may require configuration in the BIOS Setup screens. This section assumes the user is familiar with general BIOS Setup and does not attempt to describe the BIOS functions. Refer to the appropriate PC reference manuals for information about the onboard ROM-BIOS software interface.
Chapter 4 BIOS Setup Accessing BIOS Setup (Serial Console) Entering the BIOS Setup, in serial console mode, is very similar to the steps you use to enter BIOS Setup with a VGA display, except the actual keys you use. 1. Set the serial terminal, or the PC with communications software to the following settings: ♦ 115k baud ♦ 8 bits ♦ One stop bit ♦ No parity ♦ No hardware handshake 2.
Chapter 4 BIOS Setup BIOS Menus BIOS Setup Opening Screen Ampro Setup Utility for LittleBoard 550, SWxxxxxx Help for BIOS and Hardware Settings > BIOS and Hardware Settings < Reload Initial Settings Load Factory Default Settings Exit, Saving Changes Exit, Discarding Changes Use Arrow keys to change menu item, use Enter to select menu item (C) Copyright 2005, Ampro Computers, Inc. - http://www.ampro.com Figure 4-1.
Chapter 4 BIOS Setup BIOS Configuration Screen Ampro Setup Utility for LittleBoard 550, SWxxxxxx [Date & Time] 14 Jan 2005< > Date Time 10:24:34 [Drive Assignment] Drive A 1.44 MB, 3.5” Drive B (none) Drive C HDD/CF on Pri Master (none) Drive D (none) Drive E Drive F (none) Drive G (none) [Boot Order] Boot 1st Drive A: Boot 2nd Drive C: Boot 3rd CDROM (none) Boot 4th (none) Boot 5th Help for Date The Date & Time fields are updated in real-time. When you make a change, the CMOS is updated immediately.
Chapter 4 BIOS Setup ♦ Drive D – [none], [HDD/CF on Pri Master], [CDROM on Pri Master], [HDD/CF on Pri Slave], [CDROM on Pri Slave], [HDD on Sec Master], [CDROM on Sec Master], [HDD on Sec Slave], [CDROM on Sec Slave], [USB HDD], or [USB CDROM] Table 4-2. Floppy Drive BIOS Settings # of Floppy Drive(s) BIOS Settings None • Set Drives A and B to [None] (1) Non-USB Floppy • Configure Drive A to floppy drive type (For example, [1.44MB, 3.
Chapter 4 BIOS Setup • Boot Order ♦ Boot 1st – [none], [Drive A], [Drive B], [Drive C], [Drive D], [CDROM], [Alarm], or [Reboot] ♦ Boot 2nd – [none], [Drive A], [Drive B], [Drive C], [Drive D], [CDROM], [Alarm], or [Reboot] NOTE The [Alarm] option sounds beeps on the PC speaker and can be listed, like [Reboot], as the last boot device to indicate no bootable device was found. Any of the drives can be listed as a boot drive.
Chapter 4 BIOS Setup This feature allows you to use any one of the three common formats available for CompactFlash cards without having to re-format the CompactFlash card before you can use it on the LittleBoard 550. The LBA (Logical Block Address) is set as the default format because it can handle larger drives and is the newest format available, but may not be the one used to format your CompactFlash card.
Chapter 4 BIOS Setup Memory Control Options • Memory ♦ ♦ Memory Test – [Fast], [Standard], or [Exhaustive] • If this field is set to [Fast], only basic memory tests are performed during POST to shorten POST time. • If this field is set to [Standard], more than basic tests are performed, but POST time is increased. • If this field is set to [Exhaustive], more rigorous tests are performed on memory, but this takes a significant amount of time for POST to complete.
Chapter 4 BIOS Setup CAUTION To prevent system hangs or failure at extended temperatures, do not change the DRAM Refresh Rate, Fast Precharge, and Bank Interleave values, unless you fully understand the intended results. Changing any of these settings may cause the processor to run slower or fail at extended temperatures for this board. If you change any of these settings and can not recover, use the Oops! Jumper to reset the BIOS to the defaults.
Chapter 4 BIOS Setup However, connecting a Hot Cable to the other port (port not selected) overrides this field setting and activates the connected port. Connecting a Hot Cable to one of the serial ports only allows console redirection when a Hot Cable is actually connected to Serial 1 or 2. Use the modified serial cable described in Chapter 3, under Hot (Serial) Cable. USB Boot Support – [Disabled] or [Enabled] ♦ This field allows you to select any USB device as a boot device.
Chapter 4 BIOS Setup • IRQ – [none], [1], [3], [4], [5], [6], [7], [9], [10], [11], [12], [14], or [15] This field specifies the IRQ used for Serial Port 1. If this field is set to [none], then no IRQ is assigned, making it available for other devices. • Mode – [RS-232] or [RS-485] This field specifies the signal mode, RS232, or RS485, used for Serial Port 1. If [RS-485] mode is selected, the RTS signal should be used to control the direction for this port (transmit or receive).
Chapter 4 BIOS Setup • DMA – [3], [2], [1], or [0] This field specifies the DMA channel used for the parallel port (LPT 1). If the LPT 1 field is set to [Disabled], then no DMA channel is assigned, making it available for other devices. • Mode – [Standard], [SPP (bi-dir)], [EPP 1.9 + SPP], [EPP 1.7 + ECP], [EPP 1.9 + ECP], or [ECP] This field specifies the Mode used for the parallel port (LPT1).
Chapter 4 BIOS Setup • ♦ If the [CRT+LCD] is selected, the same video information is shown on both displays simultaneously. Panel Type – [640 x 480 x 18 TFT] Refer to Table 4-3 for the list of supported resolutions and flat panel types and the Software Release Notes for the signal pin assignments. Some LCD panels may require video BIOS modifications. If you would like help in setting up your LCD panel, contact Virtual Technician on the web site for assistance with the LCD panel adaptation. Table 4-3.
Chapter 4 BIOS Setup • ♦ If this field is set to [Disabled], the IRQs and DMA channels listed below can not be assigned to Plug and Play devices. PnP OS – [Disabled] or [Enabled] If this field is set to [Enabled], the BIOS makes the Plug and Play API available for Plug and Play Operating Systems. This allows the Plug and Play OS to get the Plug and Play information by calling the Plug and Play API.
Chapter 4 BIOS Setup ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ Assign IRQ 10 – [Disabled] or [Enabled] (Typically unused) • If this field is set to [Enabled], then the BIOS can assign this IRQ to a Plug and Play adapter. • If another device in the system is using this IRQ, then this field should be set to [Disabled]. Assign IRQ 11 – [Disabled] or [Enabled] (Typically ISA Bridge/Native IDE) • If this field is set to [Enabled], then the BIOS can assign this IRQ to a Plug and Play adapter.
Chapter 4 BIOS Setup ♦ ♦ ♦ ♦ 78 Assign DMA 3 – [Disabled] or [Enabled] • If this field is set to [Enabled], then the BIOS can assign this DMA channel to a Plug and Play adapter. • If another device in the system is using this DMA channel, then this field should be set to [Disabled]. Assign DMA 5 – [Disabled] or [Enabled] • If this field is set to [Enabled], then the BIOS can assign this DMA channel to a Plug and Play adapter.
Chapter 4 BIOS Setup Splash Screen Customization The LittleBoard 550 BIOS supports a graphical splash screen, which can be customized by the user and displayed on screen when enabled through the BIOS Setup Utility. The graphical image can be a company logo or any custom image the user wants to display during the boot process.
Chapter 4 BIOS Setup Use the following steps to convert and load your custom image onto the LittleBoard 550. 1. Copy the files from the LB550\software\examples\splash directory on the CD-ROM to a new directory (conversion directory) on your PC. This new conversion directory is where you intend to do the conversion and save the file. 2. Remove the read-only attributes from all the files as part of the file copying process. 3. Copy the LittleBoard 550 BIOS binary file (lb550.
Appendix A Technical Support Ampro Computers, Inc. provides a number of methods for contacting Technical Support listed in the Table A-1 below. Requests for support through the Virtual Technician are given the highest priority, and usually will be addressed within one working day. • Ampro Virtual Technician – This is a comprehensive support center designed to meet all your technical needs. This service is free and available 24 hours a day through the Ampro web site at http://ampro.custhelp.com.
Appendix A 82 Technical Support Reference Manual LittleBoard 550
Appendix B Connector Part Numbers The following table provides the connector part numbers, or the equivalent, and if applicable the ribboncable part number, used as the mating connector to the referenced connectors on the LittleBoard 550. All connectors use 0.100” (2.54mm) pin spacing unless otherwise indicated. Table B-1.
Appendix B 84 Connector Part Numbers Reference Manual LittleBoard 550
Appendix C LAN Boot Option The LAN Boot feature is optional for the LittleBoard 550 and you must contact Ampro or your sales representative for more information before you can make use of this option. The LAN Boot option requires a BIOS update to make use of the LAN Boot features. Introduction LAN Boot is supported by both Ethernet ports on the LittleBoard 550, and is based on the Preboot Execution Environment (PXE), an open industry standard.
Appendix C LAN Boot Options PXE Boot Agent BIOS Setup This section describes the BIOS settings of the third party PXE Boot agent provided by Ampro and integrated into the LittleBoard 550 firmware upgrade. The PXE Boot Agent’s BIOS setup menu and screens are used when configuring the LAN boot feature in the LittleBoard 550 BIOS. The third party PXE Boot agent provided by Ampro supports multiple boot protocols and network environments such as traditional TCP/IP, NetWare, and RPL.
Appendix C LAN Boot Options PXE Boot Agent Setup Screen Argon Managed PC Boot Agent (MBA) v4.
Appendix C LAN Boot Options • NetWare Configuration ♦ Boot Method: – [PXE], [TCP/IP], [NetWare], or [RPL] ♦ Protocol: – [802.2], [802.
Index Ampro Products CoreModule™ Family .......................................3 EnCore™ Family ...............................................4 ETX Family .......................................................3 LittleBoard™ 700 ..............................................2 LittleBoard™ 800 ..............................................3 MightyBoard™ Family ......................................3 MiniModule™ Family........................................3 ReadyBoard™ Family...............................
Index Lithium Battery RTC..................................................................59 LittleBoard 550 audio interface features ....................................53 block diagram...................................................10 boot devices .....................................................66 CompactFlash socket .......................................39 connector list....................................................12 console redirection ...........................................
Index splash screen converting image..............................................79 customer defined..............................................79 customization ...................................................79 image conversion tools ....................................80 requirements.....................................................79 supported features 168-pin SDRAM DIMM..............................7, 22 512kB flash memory........................................22 audio amplifier..............
Index 92 Reference Manual LittleBoard 550
