Specifications
ters:
(1)
Unlike
the
memory wait state control parameters (UMW.MMW.LMW). there are
no address boundaries for the
I/O.
DMA, and refresh wait state parameters.
(2) The values for
DMA
wait states
(DMA
W)
and refresh wait states
(RFW)
are inde-
pendent
of
the
values
specified
for
ordinary
memory
access
cycles
(UMW.MMW.LMW) and ordinary
I/O
access cycles (lOW).
Since
DMA
cycles generally involve both memory
AmI
I/O
devices,
the
values for
DMA
wait
states
(DMA
W)
and refresh wait states (RFW) must
be
set
to
the greatest number required
by associated memory
.Q!
I/O
devices regardless
of
the settings
of
the memory and
I/O
wait
state parameters.
For
example.
if
DMA
can occur between on-board
DRAM
(1 wait state)
and a slow
I/O
device
on
the
PC
Expansion Bus (3 wait states). then DMAW must
be
set to
3. Similarly. if
the
system has dynamic memory
on
the
PC
Expansion Bus requiring 2 wait
states, then
RFW
must
be
set to
2.
All
of
these operations are usually performed in a single command, as indicated
by
the above
examples.
SETWAIT-3ยท