Specifications

Table 5-4. ROM-BIOS Default V40 Initialization
REG
I/O ADR CONTENTS
DESCRIPTIOH
OPCN
FFFEh
00000011
Pin fU'lCtion options:
IRQ1, IRQ2, RXD,
TXD, SRDY
OPSEL FFFDh
00001111 Enable all peripherals
OPHA
FFFCh 00000000
Set High Address = OOh
DULA
FFFBh 00010000 DMAU Low Address = 10h
IULA
FFFAh 00100000 ICU Low Address = 20h
TUlA FFF9h
01000000 CTC low Address = 40h
SUlA FFF8h 11110000
SCU Low Address = FOh
WCY2 FFF6h
00001110 Wait States:
DMAU = 3
RFU
= 2
WCY1 FFFSh 01010000
Wait States:
I/O = 3 *
Upper Memory
= 0
Middle Memory = 2
lower Memory
= 1
101MB FFF4h 01010000 Wait Memory Boundaries:
low = 256k
High = 32K
RFC FFF2h 10000110 Refresh Control:
Refresh enabled
8 * 12/ 7.16 MHz
= 13.4 microsec
TCKS FFFOh 00011100 Timer Clock Control:
TCT to = TClK
TCT #1 = TelK
TCT #2 = TClK
*
Fixed at 5 wait states if W48 is jumpered to 2/3
5-6