Specifications
Table 5-3.
V40
Internal Peripheral Control Registers
I/O
ADR
NAMe
DESCRIPTION
FFFFh
Reserved
FFFEh
OPCN
on-chip Peripheral Comection register_
Selects
between
DMA3
and
V40
serial.
FFFDh
OPSEL
on-chip Peripheral Selection.
Enables
SCU,
CTC,
ICU,
and
DMAU
FFFCh
OPHA
on-chip Peripheral
High
Address.
Sets the upper byte of the
I/O
address
assigned
to
the
SCU,
CTC,
lCU,
DMAU.
FFFBh
DULA
DMAU
Low
Address.
Sets the
lower
byte of the
I/O
address
assigned
to
the
DMAU.
FFFAh
IULA
I
CU
Low
Address.
Sets the
lower
byte of the
I/O
address
assigned
to
the
ICU.
FFF9h
TULA
CTC
Low
Address.
Sets the
lower
byte of the I/O address
assigned
to
the
CTC.
FFF8h
SULA
SCU
Low
Address.
Sets the
lower
byte of the I/O address
assigned
to
the
SCU.
FFF7h
Reserved
FFF6h
WCY2
Wait
Cycles 2.
Sets the
number
of wait cycles for
DMA
and
refresh cycles.
FFF5h
wcn
Wait
Cycles 1
Sets the
number
of wait
states
for
each
of three
memory
regions and for
I/O
cycles.
FFF4h
WMB
Wait
Memory
Boundary.
Defines the boundary addresses of
the three
memory
wait
state
regions.
FFF3h
Reserved
FFF2h
RFC
Refresh Control.
Enables/Disables refresh
by
the
RFU
and
sets
the refresh
interval.
FFF1h
Reserved
FFFOh
TCKS
Timer
Clock
Selection.
Selects the clock source
(internal
or external) for the
CTC
and
the
divisor
by
which
the frequency of
the internal clock
is
divided.
5-5