Specifications
5.4
V40
INTERNAl
REGISTERS
The V
40
CPU
has the following internal controllers:
REFU
WCU
erc
SCU
lCU
DMAU
Refresh Control Unit
Wait State Control Unit
Counter
/Timer
Controller
Serial Control
Unit
Interrupt Control Unit
DMA
Control Unit
The
V 40 accesses the internal peripherals using normal
I/O
addressing.
The
addresses
assigned
to
these internal peripherals
are
not available for general use. Note, though, that
these addresses
are
situated
at
the very
top
of
the 16-bit
I/O
address space. Since
the
PC
architecture only uses the lowest
1024
I/O
addresses, there is no conflict.
Table 5-3 contains a list
of
the
internal V
40
peripheral addresses and a brief description
of
their function. These
are
for reference only.
To
program any
of
these registers, you must
refer to the V40
User's Manual for the detailed bit definitions.
5.5
V40
INITIALIZATION
Table 5-4 describes the state
of
the internal peripheral control ports
after
they
have
been
initialized by the Little
Board/PC's
ROM-BIOS.
The
description field shows the resulting
state
of
the internal peripherals.
The wait state values used in the
ROM-BIOS are intended to allow the system to boot and
begin
operation
from the widest possible range
of
on-board and
bus
devices.
Any
of
these
values may
be
changed by writing a short program that outputs ditTerent values to the indicat-
ed
I/O
addresses. Such a program
is
provided as part
of
the
Little
Board/PC
Support Soft-
ware, and should be used to set appropriate values following system boot.
This
can
be
done
as part
of
the DOS AUTOEXEC.BAT function.
5-4