Specifications
DRAM
refresh in a standard
PC
is
accomplished
by
using erc
channell,
DMA
channel 0,
and
several additional external devices. On the Little BoardIPC, these
are
not
required due
to
the
availability
of
a
dedicated
refresh
controller
within
the
V 40
CPU.
In
addition,
the
V40's
refresh
request
(REFRQ)
signal is
used
to
generate
the
DACKO signal
on
the
PC
Expansion Bus, providing a refresh signal for expansion cards plugged into the bus.
Like
the
standard
PC,
the
Little
Board/PC
includes a parity
bit
for
each
byte
of
DRAM
storage.
The
parity bit is set
or
reset when a byte
is
written to the DRAM,
and
tested when
the byte is
read.
(The
parity
bit is
set
true
if
there
is
an
odd
number
of
1's
in
the
memory
byte,
and
set
false if
there
is
an
even
number.)
The
parity
control
logic is
contained
within
ASIC2.
When
a parity fault
is
detected, ASIC2 generates
an
NMI to the
CPU,
whereupon
PC-DOS displays
an
error
message and halts the computer.
Jumper
W21
on
the
board
allows you
to
use 8-bit
SIMM
DRAM
strips (without
the
parity
bit) when it is shorted.
The
SIMM
DRAM
requires
at
least one wait state for 150 nanoseconds access time DRAM's.
It
is not possible to use faster DRAM's to eliminate this wait state.
4.5.2
EPROM
Socket
(U21)
The
socket at U21 normally contains a 27256 (32K byte)
EPROM,
programmed with a
PC
compatible ROM-BIOS and
Ampro
SCSI/BIOS. This socket is enabled with a strobe gener-
ated
by
ASIC1 for system memory reads in the address interval F8000h through FFFFFh.
Note that the Little
Board/PC
must have
an
EPROM
installed in this socket to provide the
V4O's
startup
jump
vector.
At
startup (following reset), the V40 executes the instruction
at
memory location FFFFOh, which is usually a
jump
to the beginning
of
the system initialization
code.
Devices with
an
access time
of
250 nanoseconds
or
less can
be
used without wait states.
4.5.3
Byte-Wide
Sockets
(U15
and
U26)
The
two 28-pin byte-wide
memory
sockets
at
U15
and
U26
support
a variety
of
28-pin
JEDEC
pinout memory devices, including
EPROM,
static RAM,
EEPROM,
page-addressed
EPROM,
and nonvolatile
RAM
(NOVRAM) modules
and
cartridges.
Chapter
2 includes a
table
indicating
the
types
and
capacities
of
the
memory
devices
each
socket
will
hold.
Ampro's
solid
state
disk
(SSD)
support
within
the
ROM-BIOS
and
optional
SSD
support
software
treats
these
sockets
as
one
or
two
DOS
disk devices, containing
as
much
as
1
megabyte
of
SSD storage (both sockets combined).
U15 is enabled with a strobe generated
by
ASIC1, conditioned
by
the board's memory control
logic, for system
meinory
reads
or
writes
in
the
memory
address
interval
FOOOOh
through
F7FFFh.
The
confIguration
of
a set of jumpers determines whether the strobe for this socket
decodes a 32K
or
8K address block, and whether the device is read-only
or
read/write,
and
what type
of
device is installed.
U26 is enabled with a strobe generated by the board's memory control logic, for system reads
within the address interval
EOOOOh
through EFFFFh. A number
of
board
jumper
options
are
provided
to
confIgure the starting memory address (eight choices)
and
installed device type.
4-9