Specifications

At 4.77 MHz (a standard PC clock rate), a clock period is approximately 210
nsec. Memory accesses on a PC are four cycles long, or 840 nanoseconds.
At 7.16 MHz (the clock rate of the Little Board/PC), a clock period is
approximately
140 nsec. Therefore, to calculate the factor needed to emu-
late the standard PC's timing on the Little Board/PC, divide 840 by 140,
which results in a requirement for
six 7.16 MHz cycles per memory access. .
This means that two wait states should be added to each memory access
cycle.
It is also possible to approximate the I/O timing of a standard PC by adding wait states. In
the standard 4.77 MHz
PC, all I/O cycles have one wait state and therefore take five clock
cycles. A calculation similar to that shown above for
PC expansion bus memory accesses
results in a requirement for three wait states, to simulate standard PC I/O accesses on the PC
Expansion Bus.
Onboard DRAM memory timing requires that refresh cycles have a single wait state.
If
slower DRAM memory is added to the system via the PC expansion bus, the number of re-
fresh wait states may have to be increased, up to the available maximum of three.
Little
Board/PC DMA transfers require either 9 or 5 cycles, depending on the setting of
W48. Regardless of the setting of W48, 4 cycles for the DMA transfer occur. If W48 is
jumpered to 2/3, 5 additional wait states are automatically added
by the board's hardware. If
W48 is jumpered to 1/2, one or more additional wait states are added by the V4O's wait state
logic.
The Ampro SETWAIT utility is typically used to initialize the V4O's wait state logic. A
single additional wait state is usually sufficient unless there are slow devices present on the
PC expansion bus.
Check the specifications of any expansion cards you will be using, to see if additional wait
states are actually required. Most expansion boards are now designed to be used with "turbo"
PC's and ATs, and should handle the Little Board/PC's fast bus access without the requirig
additional wait states.
4.5 ONBOARD MEMORY
The Little Board/PC provides sockets for four categories of onboard memory, including
dynamic RAM (DRAM),
EPROM, and byte-wide volatile and nonvolatile static RAM.
These are now discussed further.
4.5.1 DRAM Sockets
The board has three positions for "SIMM" DRAM modules each of which consist of nine
256K x 1 bit DRAM IC's (or two 256 x 4 bit and one 256K x 1 bit IC's) and provide eight bits
of RAM plus parity.
Control timing for the three
SIMM DRAM modules is generated by ASIC!. It multiplexes
the address lines into row and column addresses, and generates the required RAS and
CAS
signal timing. A single RAS signal and three CAS signals (one for each SIMM module) are
provided.
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