Specifications

Table 4-1. DMA Channel Remapping
STANDARD PC
ACTUAL V40 ASSIGNMENT
DNA CHANNEL
DNA CHANNEL
1
0 Available to user
2 1 Floppy disk controller
3
2
SCSI controller (fixed disk)
Since DMA channel 0 in a PC is used for DRAM refresh, the PC Expansion Bus does not
provide a pin for
"DRQO." "DACKO" does appear on the PC Expansion bus, to let expansion
cards know when a DRAM refresh
cycle is taking place. The Little Board/PC also provides a
DACKO signal, based on the V4O's DRAM refresh signal.
One unique characteristic of the V 40'S DRAM refresh logic is that it will often do "burst"
refreshes in which several refreshes occur back-to-back with no other
CPU cycles intervening.
Be sure not to use PC bus expansion cards whose proper functioning depends
on regular 15
microsecond refresh pulses.
Emulation Performance
Although the board's 8237 A emulation logic allows the board's DMA controller to be ac-
cessed like a
PC DMA controller in the "normal" manner, the board's DMA controller can
actually
be accessed in two ways:
(1) Indirectly (via the 8237A emulation logic and
BIOS routines), as an 8237A, using the
standard PC channel assignments and
I/O addresses.
(2) Directly, as a
V40 DMA controller (which it is!), using the actual channel assign-
ments (see Table 4-1) and
I/O addresses (see Chapter 5).
Since the DMA controller's internal registers are only accessed once for each block of
DMA
data transferred, the overall system performance is not significantly affected by using indirect
access via the 8237 A emulation function. However, to obtain maximum performance,
the
V 40 DMA controller's internal registers can be directly accessed instead.
4.4.4 Wait State Control
The number of wait states for memory, I/O, refresh, and DMA are all independently con-
trolled by the programming
of a group of internal registers within the V40. As a set, these
are called the WCU or Wait Control Unit. Up to three wait states can be inserted. In the
case
of memory, the address space can be divided into three regions, and each region can be
independently specified. The default programming of the V 40's WCU is shown in Chapter 5.
The requirements for on-board memory wait states are discussed in the sections on onboard
memory options, below.
If memory devices are to be added via a plug-in card on the PC bus,
it may be necessary to increase the number
of wait states.
In general, two memory wait states are required to approximate the timing of a standard 4.77
MHz PC's expansion bus memory access cycle.
This is calculated as follows:
4-7