User`s manual

DIGITAL-LOGIC AG MSLB-P5 Manual V0.3
PRELIMINARY 25
SD[O..15], input/output
These signals provide bus bits 0 through 15 for the microprocessor, memory, and I/0 devices. DO is
the least-significant bit and D15 is the most significant bit. All 8-bit devices on the I/O channel should
use DO through D7 for communications to the microprocessor. The 16-bit devices will use DO through
D15. To support 8-bit device, the data on D8 through D15 will be gated to DO through D7 during 8-bit
transfers to these devices; 16-bit microprocessor transfers to 8-bit devices will be converted to two 8-
bit transfers.
/SMEMR input/output
These signals instruct the memory devices to drive data onto the data bus for the first MByte. /SMEMR
is active on all memory read cycles. /SMEMR may be driven by any microprocessor or DMA controller
in the system. When a microprocessor on the I/0 channel wishes to drive /SMEMR, it must have the
address lines valid on the bus for one system clock period before driving /SMEMR active. The signal is
active low.
/SMEMW, input/output
These signals instruct the memory devices to store the data present on the data bus for the first
MByte. /SMEMW is active in all memory read cycles. /SMEMW may be driven by any microprocessor
or DMA controller in the system. When a microprocessor on the I/O channel wishes to drive /SMEMW,
it must have the address lines valid on the bus for one system clock period before driving /SMEMW
active. Both signals are active low.
SYSCLK, output
This is a 8 MHz system clock. It is a synchronous microprocessor cycle clock with a cycle time of 167
nanoseconds. The clock has a 50% duty cycle. This signal should only be used for synchronization. It
is not intended for uses requiring a fixed frequency.
TC output
Terminal Count provides a pulse when the terminal count for any DMA channel is reached. The TC
completes a DMA-Transfer. This signal is expected by the onboard floppy disk controller.
/OWS, input
The Zero Wait State (/OWS) signal tells the microprocessor that it can complete the present bus cycle
without inserting any additional wait cycles. In order to run a memory cycle to a 16-bit device without
wait cycles, /OWS is derived from an address decode gated with a Read or Write command. In order
to run a memory cycle to an 8-bit device with a minimum of one-wait states, /OWS should be driven
active one system clock after the Read or Write command is active, gated with the address decode for
the device. Memory Read and Write commands to an 8-bit device are active on the falling edge of the
system clock. /OWS is active low and should be driven with an open collector or tri-state driver capa-
ble of sinking 2OmA.
12V +/- 5%
used only for the flatpanel backligth supply only.
GROUND = 0 Volt
used for the entire system.
VCC, +5V +/- 0.25 Volt
3-4 Amp. nominal, peak current of HD, SCSI-Devices and Cache could go up to 8 Amp..